EE141_HW8_sol - UNIVERSITY OF CALIFORNIA, BERKELEY College...

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UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences Elad Alon Homework #8 Solutions EECS141 PROBLEM 1: DOMINO LOGIC AND CHARGE SHARING a) Implement the logic shown below as a single complex, dynamic gate (with four inputs) followed by an inverter. A B D X C Solution: X X A B D X C A B D C A B D C After restructuring the logic we can now implement this logic using a single complex dynamic gate followed by an inverter:
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b) What pattern of the inputs P 1 , G 0 , and G 1 results in the worst-case drop in voltage on node G 1:0 _b due to charge sharing for the gate shown below? Assuming V DD = 1.2V, C G = 2fF/μm, and C D = 1.5fF/μm, what is this worst-case voltage? Solution: The worst case charge sharing occurs under the following input pattern: P 1 G 0 3um 2um 4um clk G 1 clk G 1:0 _b y x 1.2V 0V 0V 1.2V 1.2V P 1 G 0 clk G 1 clk G y x 0V 0V 0V P 1 G 0 clk G 1 clk G y x 1.2V 1.2V 1.2V Previous Cycle Current Cycle In the evaluation phase of the previous cycle, G 0 was on and discharges node x to 0. In the precharge phase of the current cycle, P
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This note was uploaded on 01/11/2011 for the course EE 141 taught by Professor Staff during the Spring '08 term at University of California, Berkeley.

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EE141_HW8_sol - UNIVERSITY OF CALIFORNIA, BERKELEY College...

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