EE141_HW9

EE141_HW9 - UNIVERSITY OF CALIFORNIA, BERKELEY College of...

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UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences Elad Alon Homework #9 EECS141 (Optional) PROBLEM 1: LOGIC STYLES Problems 3)b) and 3)c) from the EE141 Fall07 Midterm #2 (available on the web). PROBLEM 2: FLIP-FLOP TIMING Problem #4 from the EE141 Fall08 Final (available on the web). PROBLEM 3: “PULSED” LATCH TIMING Consider the simple state machine shown above. A, B, and C represent combinational logic blocks with the following properties: t logic,minA = 200 ps; t logic,maxA = 1 ns; t logic,minB = 300 ps; t logic,maxB = 2 ns; t logic,minC = 100 ps; t logic,maxC = 0.5 ns; The L-units represent positive latches clocked by φ (i.e., the latches are transparent when φ is high). These latches have a setup time of 150 ps and a t d-q delay of 250 ps (when the latch is transparent). The clock to output delay t clk-q is 100 ps, and t hold is 100 ps. The clock φ has a period T clk and is high for a duration of T on – in other words, the duty cycle of the clock is T on / T clk .
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EE141_HW9 - UNIVERSITY OF CALIFORNIA, BERKELEY College of...

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