Midterm1-f99

Midterm1-f99 - University of California College of...

Info iconThis preview shows pages 1–3. Sign up to view the full content.

View Full Document Right Arrow Icon
EECS 141: FALL 99 — MIDTERM 1 1 University of California College of Engineering Department of Electrical Engineering and Computer Science J. M. Rabaey TuTh9:30-11am B. Nikolic ee141@eecs EECS 141: FALL 99 — MIDTERM 1 For all problems, you can assume the following transistor parameters (unless otherwise mentioned): NMOS: V Tn = 0.4, k ’ n = 115 μ A/V 2 , V DSAT = 0.6V, λ = 0, γ = 0.4 V 1/2 , 2 Φ F = -0.6V PMOS: V Tp = -0.4V, k ’ p = -30 μ A/V 2 , V DSAT = -1V, λ = 0, γ = -0.4 V 1/2 , 2 Φ F = 0.6V NAME Last First GRAD/UNDERGRAD Total Problem 2: Problem 1: Problem 3:
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
EECS 141: FALL 99 — MIDTERM 1 2 PROBLEM 1: Transient Response Consider the circuit of FIG. 1. Use the transistor parameters indicated on the first page of the midterm, with one modifica- tion. For both PMOS and NMOS, assume that γ = 0. V DD = 2.4 V . C L 1 = C L 2 = 20 fF. Leakage effects should not be consid- ered in this question. a. Assume that the initial voltage on V out = 0. A step from 0 to V DD is applied at the input. Determine the final voltage at V out . b. Subsequently, a negative step (from V DD to 0 V) is applied at the input. Determine again the final voltage at V out .
Background image of page 2
Image of page 3
This is the end of the preview. Sign up to access the rest of the document.

Page1 / 8

Midterm1-f99 - University of California College of...

This preview shows document pages 1 - 3. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online