lecture4 - ECE520 VLSI Design Lecture 4: Device Scaling...

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1 ECE520 - Lecture 4 Slide: 1 University of New Mexico Office: ECE Bldg. 230B Office hours: Tuesday 2:00-3:00PM or by appointment E-mail: [email protected] Payman Zarkesh-Ha ECE520 – VLSI Design Lecture 4: Device Scaling Issues & Advanced MOS ECE520 - Lecture 4 Slide: 2 University of New Mexico Review of Last Lecture Overview of “Static Parameters of Long Channel MOSFET” “Dynamic Parameters of Long Channel MOSFET” MOSFET Parasitic Capacitances Overlap capacitances Channel capacitances Junction capacitances
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2 ECE520 - Lecture 4 Slide: 3 University of New Mexico Today’s Lecture Device Modeling Issues for “Short Channel” MOS Short Channel Effects Source-Drain resistance Subthreshold conduction Velocity saturation Mobility degradation Threshold voltage rolloff DIBL effect Punch through Hot electron Narrow channel effect Device Scaling Issues ECE520 - Lecture 4 Slide: 4 University of New Mexico When the channel length becomes comparable to other dimensions like depth of the source/drain junctions and the width of the depletion regions the “long-channel” approximations made previously break down Assumptions such as, current flows only on surface, electric field is only in the direction of current flow, etc., are no longer true Such a short channel device can not be adequately described by simple one dimensional model. Hence, a two dimensional model is widely used. With transistor scaling, junctions are made shallower & contacts windows are made smaller while their depth is increased Device Scaling Issues
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3 ECE520 - Lecture 4 Slide: 5 University of New Mexico With transistor scaling, junctions are made shallower & contacts windows are made smaller while their depth is increased Technology and design objective is to reduce source-drain resistance Often source drain regions are covered by titanium or tungsten (silicidation) to reduce the resistance L D W Drain V GS_eff R S R S Source-Drain Resistance ECE520 - Lecture 4 Slide: 6 University of New Mexico Subthreshold Conduction I DS does not equal to zero even with V GS = 0 To get I DS =0 need V DS =0 This is known as subthreshold conduction I D (mA) Log(I ) (mA)
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4 ECE520 - Lecture 4 Slide: 7 University of New Mexico Subthreshold Conduction Subthreshold conduction happens because of parasitic bipolar transistor [i.e. n+(source),p(bulk),n+(drain)] The current in subthreshold region can be approximated by: I off is defined as the I DS when V GS =0 and high V DS This is the transistor source to drain leakage (dominant leakage) Sum of I off across the die is the static power component Static power is a limiting component of the total power (particularly for mobile markets) Key points: I DS depends exponentially on V GS below threshold I off increases 3-10x per process generation (high performance) I off increases 8-12x per 100ºC  DS q / kT V q / nkT V 0 D V 1 e 1 e I I DS GS
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This note was uploaded on 01/11/2011 for the course ECE 520 taught by Professor Zarkesh-ha,p during the Fall '08 term at New Mexico.

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lecture4 - ECE520 VLSI Design Lecture 4: Device Scaling...

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