lecture6 - ECE520 VLSI Design Lecture 6: Dynamic Behavior...

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1 ECE520 – Lecture 6 Slide: 1 University of New Mexico Office: ECE Bldg. 230B Office hours: Tuesday 2:00-3:00PM or by appointment E-mail: payman@ece.unm.edu Payman Zarkesh-Ha ECE520 – VLSI Design Lecture 6: Dynamic Behavior of CMOS Inverter ECE520 – Lecture 6 Slide: 2 University of New Mexico Review of Last Lecture Static Behavior of CMOS Inverter Switching threshold Noise margin CMOS Voltage-Transfer Characteristic (VTC) CMOS Inverter Robustness Device variations V dd scaling (minimum supply voltage)
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2 ECE520 – Lecture 6 Slide: 3 University of New Mexico Today’s Lecture Dynamic Behavior of CMOS Inverter Computing the capacitances Propagation delay model Dynamic power Power due to direct-path current Leakage power Some design techniques ECE520 – Lecture 6 Slide: 4 University of New Mexico Definition: Propagation Delay V in V out t pHL t pLH V in V out C out C in R p, R n Definition of propagation delay is delay from where input crosses 50%Vdd to where output crosses 50%Vdd Remember: the value of 50%Vdd is from switching threshold voltage (V M ) t pHL is propagation delay when output switches from “High to Low” t pLH is propagation delay when output switches from “Low to High” To compute delay, the inverter must be simplified
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3 ECE520 – Lecture 6 Slide: 5 University of New Mexico C DBp C GBp C GSp C GDp C SBp C SBn C GBn C GDn C GSn C DBn V DD GND C in C out Parasitic Capacitances Components Miller Caps     GBn GSn GDn GBp GSp GDp in C C C C C C C     DBn GDn DBp GDp out C C 2 C C 2 C ECE520 – Lecture 6 Slide: 6 University of New Mexico Output Caps: Miller Capacitances C GD is often the most important component, because They are often large Since both the input and output are moving in opposite direction, the effective capacitance is doubled (miller effect) This is also a source of overshoot in the output waveform (feed forward effect) Assuming very fast input rise time, the devices are either cutoff or saturation (for the most part). In either case C GD is only the overlap capacitance i.e. (refer to lecture 3) Feed forward effect d ox GDOV GD X WC C C C DBp C GBp C GSp C GDp C SBp C SBn C GBn C GDn C GSn C DBn V DD GND C out Miller Caps
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4 ECE520 – Lecture 6 Slide: 7 University of New Mexico Output Caps: C DB Junction Capacitances C DB is drain junction capacitances of NMOS and PMOS They are non-linear voltage dependent capacitances (refer to lecture 3) To simplify calculations, we assume a constant value for C
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This note was uploaded on 01/11/2011 for the course ECE 520 taught by Professor Zarkesh-ha,p during the Fall '08 term at New Mexico.

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lecture6 - ECE520 VLSI Design Lecture 6: Dynamic Behavior...

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