lecture8 - 1 ECE520 Lecture 8 Slide: 1 University of New...

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Unformatted text preview: 1 ECE520 Lecture 8 Slide: 1 University of New Mexico Office: ECE Bldg. 230B Office hours: Tuesday 2:00-3:00PM or by appointment E-mail: payman@ece.unm.edu Payman Zarkesh-Ha ECE520 VLSI Design Lecture 8: Interconnect Manufacturing and Modeling ECE520 Lecture 8 Slide: 2 University of New Mexico Review of Last Lecture CMOS Manufacturing Process Front-end Process Modern CMOS Process Salisidation Low Doped Drain (LDD) Shallow Trench Isolation (STI) 2 ECE520 Lecture 8 Slide: 3 University of New Mexico Todays Lecture Interconnect Manufacturing Process Back-end Process (Conventional) Back-end Process (Modern Dual Damascene) Interconnect Modeling Parasitic Capacitance Parasitic Resistance Parasitic Inductance Delay Estimation Techniques ECE520 Lecture 8 Slide: 4 University of New Mexico Conventional Interconnect Process 21.Deposit ILD (SiO 2 ) 22.Pattern and etch contact holes 23.Sputter on M1 24.Pattern and etch M1 FOX (SiO 2 ) N-Well P-Substrate n+ n+ n+ p+ p+ p+ FOX (SiO 2 ) 3 ECE520 Lecture 8 Slide: 5 University of New Mexico Problem with Conventional Process Adding more metal layers increases unevenness of the surface. Uneven surface (topography) causes yield problem with metal mask. Because of uneven surface, conventional interconnect process (reflow) requires several restriction on the layout design. Stacking via is prohibited in conventional process. The maximum number of metal layers is limited to 3. ECE520 Lecture 8 Slide: 6 University of New Mexico Advanced VLSI technology requires many layers of interconnects As transistor density/quantity increases there is more and more need for interconnect Planarization is therefore needed for back-end process in advanced VLSI technology....
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This note was uploaded on 01/11/2011 for the course ECE 520 taught by Professor Zarkesh-ha,p during the Fall '08 term at New Mexico.

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lecture8 - 1 ECE520 Lecture 8 Slide: 1 University of New...

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