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Unformatted text preview: 1 ECE520 Lecture 9 Slide: 1 University of New Mexico Office: ECE Bldg. 230B Office hours: Tuesday 2:00-3:00PM or by appointment E-mail: email@example.com Payman Zarkesh-Ha ECE520 VLSI Design Lecture 9: Design Rules ECE520 Lecture 9 Slide: 2 University of New Mexico Review of Last Lecture Interconnect Manufacturing Process Back-end Process (Conventional) Back-end Process (Modern Dual Damascene) Interconnect Modeling Parasitic Capacitance Parasitic Resistance Parasitic Inductance Delay Estimation Techniques 2 ECE520 Lecture 9 Slide: 3 University of New Mexico Todays Lecture Review of output resistance of an inverter Overview of Design Rules What are design rules? Why have design rules? Typical design rules ECE520 Lecture 9 Slide: 4 University of New Mexico Interface between the circuit designer and process engineer Guidelines for constructing process masks Unit dimension: minimum feature size (transistor gate length) scalable design rules: lambda parameter absolute dimensions: micron rules Rules constructed to ensure that design works even when small...
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This note was uploaded on 01/11/2011 for the course ECE 520 taught by Professor Zarkesh-ha,p during the Fall '08 term at New Mexico.
- Fall '08