lecture11

# lecture11 - ECE520 VLSI Design Lecture 11: Combinational...

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1 ECE520 – Lecture 11 Slide: 1 University of New Mexico Office: ECE Bldg. 230B Office hours: Tuesday 2:00-3:00PM or by appointment E-mail: [email protected] Prof. Payman Zarkesh-Ha ECE520 – VLSI Design Lecture 11: Combinational Static Logic ECE520 – Lecture 11 Slide: 2 University of New Mexico Review of Last Lecture L-Edit Demo Layout Techniques Design for density Design for performance Design for reliability

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2 ECE520 – Lecture 11 Slide: 3 University of New Mexico Today’s Lecture Combinational Logic Logic Design Transistor Sizing Delay Analysis ECE520 – Lecture 11 Slide: 4 University of New Mexico Combinational versus Sequential Logic Combinational Logic: Output is a function of present inputs (delayed by the propagation delay) i.e., do not contain memory Implements logic functions like NAND, NOR, XOR, Multiplex or any complex functions such as Decoder, adder, shifter Sequential Logic: Implement memory Stores past values Edge sensitive: Flip-flops Level sensitive: Latches Combinational Logic Circuit Out In Combinational Logic Circuit Out In State Combinational Logic: Out=f(in) sequential Logic: Out=f(in,previous_in)
3 ECE520 – Lecture 11 Slide: 5 University of New Mexico Static CMOS Logic Gate V DD F(In1,In2,…InN) In1 In2 InN In1 In2 InN PUN PDN PMOS only NMOS only PUN and PDN are dual logic networks Static Logic is a gate where the output is maintained at 0 or 1 as long as power is applied PUN and PDN are dual (Complimentary) to drive the output from 0 to 1 and 1 to 0 full rail (VSS to VDD) ECE520 – Lecture 11 Slide: 6 University of New Mexico

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## This note was uploaded on 01/11/2011 for the course ECE 520 taught by Professor Zarkesh-ha,p during the Fall '08 term at New Mexico.

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lecture11 - ECE520 VLSI Design Lecture 11: Combinational...

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