lecture12 - ECE520 VLSI Design Lecture 12: Gate Sizing...

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1 ECE520 – Lecture 12 Slide: 1 University of New Mexico Office: ECE Bldg. 230B Office hours: Tuesday 2:00-3:00PM or by appointment E-mail: payman@ece.unm.edu Payman Zarkesh-Ha ECE520 – VLSI Design Lecture 12: Gate Sizing (Inverter Chain) ECE520 – Lecture 12 Slide: 2 University of New Mexico Review of Last Lecture Combinational Logic Logic Design Transistor Sizing Delay Analysis
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2 ECE520 – Lecture 12 Slide: 3 University of New Mexico Today’s Lecture Quiz #2 Gate Sizing (Inverter Chain) ECE520 – Lecture 12 Slide: 4 University of New Mexico Sizing Logic Path for Speed Frequently, input capacitance of a logic path is constrained Logic also has to drive some capacitance Example: ALU load in an Intel’s microprocessor is 0.5pF How do we size the ALU data path to achieve maximum speed? Wide gate to drive a large load must be driven in turn Large block inputs “push their load into the chip”
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3 ECE520 – Lecture 12 Slide: 5 University of New Mexico Definition: Fan-out 3X
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lecture12 - ECE520 VLSI Design Lecture 12: Gate Sizing...

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