lecture13 - ECE520 VLSI Design Lecture 13: Logical Effort...

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1 ECE520 – Lecture 13 Slide: 1 University of New Mexico Office: ECE Bldg. 230B Office hours: Tuesday 2:00-3:00PM or by appointment E-mail: payman@ece.unm.edu Payman Zarkesh-Ha ECE520 – VLSI Design Lecture 13: Logical Effort ECE520 – Lecture 13 Slide: 2 University of New Mexico Review of Last Lecture Quiz Gate Sizing (Inverter Chain)
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2 ECE520 – Lecture 13 Slide: 3 University of New Mexico Today’s Lecture Motivation Model the delay of one gate The delay of a chain of gates (multistage) Branching Minimum delay Best number of stages and gate sizing Examples Limitations ECE520 – Lecture 13 Slide: 4 University of New Mexico Logical Effort Motivation Sizing of a chain of inverters Geometric progression How about more complex logic? Logical Effort objectives: Quick and “back of the envelope” sizing Make trade-off between circuits Reference: I. Sutherland, B. Sproull, D. Harris, Logic Effort - designing fast CMOS Circuits, Academic Press, 1999
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3 ECE520 – Lecture 13 Slide: 5 University of New Mexico Why Do We Need Logical Effort? B A AB F V DD V DD A B F V DD A A F 1 22 2 2 2 11 4 4 Inverter 2-input NAND 2-input NOR All three gates have the same drive strength. But, how about input capacitance? ECE520 – Lecture 13 Slide: 6 University of New Mexico Delay Scaling with Device Size Let’s model an inverter with a resistor If we scale the inverter by a ratio of S ( i.e. R=K 1
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This note was uploaded on 01/11/2011 for the course ECE 520 taught by Professor Zarkesh-ha,p during the Fall '08 term at New Mexico.

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lecture13 - ECE520 VLSI Design Lecture 13: Logical Effort...

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