lecture14 - ECE520 VLSI Design Lecture 14: Pseudo Logic and...

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1 ECE520 – Lecture 14 Slide: 1 University of New Mexico Office: ECE Bldg. 230B Office hours: Tuesday 2:00-3:00PM or by appointment E-mail: payman@ece.unm.edu Payman Zarkesh-Ha ECE520 – VLSI Design Lecture 14: Pseudo Logic and Pass-Transistor Logic ECE520 – Lecture 14 Slide: 2 University of New Mexico Review of Last Lecture Midterm Exam
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2 ECE520 – Lecture 14 Slide: 3 University of New Mexico Today’s Lecture Midterm Exam Review Other Types of Static Logic Pseudo logic Pass-transistor logic ECE520 – Lecture 14 Slide: 4 University of New Mexico Ratioed Logic One way to reduce the number of transistors in complex logic gate is to replace pull up network (PUN) with a resistor. Here are some examples: V DD V SS PDN In 1 In 2 In 3 F R L Load V DD V SS In 1 In 2 In 3 F V DD V SS PDN In 1 In 2 In 3 F V SS PDN Resistive Depletion Load PMOS Load (a) resistive load (b) depletion load NMOS (c) pseudo-NMOS V T < 0
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3 ECE520 – Lecture 14 Slide: 5 University of New Mexico V DD ABCD F C L V OH = V DD
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lecture14 - ECE520 VLSI Design Lecture 14: Pseudo Logic and...

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