lecture17 - ECE520 VLSI Design Lecture 17: Sequential Logic...

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1 ECE520 – Lecture 17 Slide: 1 University of New Mexico Office: ECE Bldg. 230B Office hours: Tuesday 2:00-3:00PM or by appointment E-mail: payman@ece.unm.edu Payman Zarkesh-Ha ECE520 – VLSI Design Lecture 17: Sequential Logic ECE520 – Lecture 17 Slide: 2 University of New Mexico Review of Last Lecture Project Review Adders: A Basic Arithmetic Building Block Ripple-Carry Adder Mirror Adder Transmission Gate Adder Carry Bypass Adder Carry-Select Adder Carry Lookahead Adder
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2 ECE520 – Lecture 17 Slide: 3 University of New Mexico Today’s Lecture Sequential Logic Latches and Flip-Flops Timing Characteristics Design of Latches and Flip-Flops Setup and Hold Time Issues ECE520 – Lecture 17 Slide: 4 University of New Mexico Design of Finite State Machine (FSM) Sequential logics are common digital circuits The next state is determined based on the current state and the current inputs In this lecture we focus on designing the flip-flop or registers COMBINATIONAL LOGIC Registers Outputs Next state CLK QD Current State Inputs
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3 ECE520 – Lecture 17 Slide: 5 University of New Mexico Latches and Flip-Flops Latches store data when clock is low Flip-flops or registers store data when clock rises Usually flip-flops are build by using two latches (we will explain later) D Clk Q D Clk Q Clk Clk D D QQ Latch Flip-Flop ECE520 – Lecture 17 Slide: 6 University of New Mexico t CLK t D t c 2 q t hold t su t Q DATA STABLE DATA STABLE Register CLK DQ Timing Characteristics of Registers Setup time (t su ) is the time that data (D) must be valid before clock transition Hold time (t hold ) is the time that data (D) must remain valid after clock transition Propagation delay (t C2Q ) is the delay time that the data (D) is copied to output (Q) with reference to clock edge
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4 ECE520 – Lecture 17 Slide: 7 University of New Mexico Minimum Cycle Time Constraints: T t C2Q + t Logic + t su Worst case is when receiving edge arrives early This constraint set the limit to maximum clock frequency that the circuit will be operable Hold Time Constraints: t (C2Q, CD) + t (Logic, CD) > t hold CD is contamination delay (fastest possible delay) This is a race between data and clock If this constraint doesn't hold the circuit is not functional at any clock freq.
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lecture17 - ECE520 VLSI Design Lecture 17: Sequential Logic...

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