lecture18 - ECE520 VLSI Design Lecture 18: Timing Issues...

Info iconThis preview shows pages 1–4. Sign up to view the full content.

View Full Document Right Arrow Icon
1 ECE520 – Lecture 18 Slide: 1 University of New Mexico Office: ECE Bldg. 230B Office hours: Tuesday 2:00-3:00PM or by appointment E-mail: payman@ece.unm.edu Payman Zarkesh-Ha ECE520 – VLSI Design Lecture 18: Timing Issues ECE520 – Lecture 18 Slide: 2 University of New Mexico Review of Last Lecture Sequential Logic Latches and Flip-Flops Timing Characteristics Design of Latches and Flip-Flops Setup and Hold Time Issues
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
2 ECE520 – Lecture 18 Slide: 3 University of New Mexico Today’s Lecture Timing Issues Critical Path False Path Clock Skew Clock Jitter ECE520 – Lecture 18 Slide: 4 University of New Mexico Pipelined Data path Circuit Flip flops synchronize data at each pipe stage start and finish Logic between them is combinational Since each stage begins and ends on a clock edge we can divide and conquer to determine the system timing This is called “timing analysis” DQ FF1 In Combinational Logic FF2 Combinational Logic FF3 CLK
Background image of page 2
3 ECE520 – Lecture 18 Slide: 5 University of New Mexico Timing Analysis Measure each path through the logic between FF’s We really only care about the longest path, called maximum delay for setup Similarly, we only care about the shortest path, called minimum delay (or contamination delay) for hold The path that gives the maximum delay on the whole chip is called “critical path” Minimum delay path Maximum delay path ECE520 – Lecture 18 Slide: 6 University of New Mexico False Path Be careful! If a critical path cannot be exercisable, it is a “false path”.
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 4
This is the end of the preview. Sign up to access the rest of the document.

Page1 / 9

lecture18 - ECE520 VLSI Design Lecture 18: Timing Issues...

This preview shows document pages 1 - 4. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online