1ECE520 – Lecture 18Slide: 1University of New MexicoOffice: ECE Bldg. 230BOffice hours: Tuesday 2:00-3:00PM or by appointmentE-mail: [email protected]Payman Zarkesh-HaECE520 – VLSI DesignLecture 18: Timing IssuesECE520 – Lecture 18Slide: 2University of New MexicoReview of Last LectureSequential Logic●Latches and Flip-Flops●Timing Characteristics●Design of Latches and Flip-Flops●Setup and Hold Time Issues
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2ECE520 – Lecture 18Slide: 3University of New MexicoToday’s LectureTiming Issues●Critical Path●False Path●Clock Skew●Clock JitterECE520 – Lecture 18Slide: 4University of New MexicoPipelined Data path CircuitFlip flops synchronize data at each pipe stage start and finishLogic between them is combinationalSince each stage begins and ends on a clock edge we can divide and conquer to determine the system timingThis is called “timing analysis”DQFF1InCombinationalLogicDQFF2CombinationalLogicDQFF3CLK