lecture20 - ECE520 VLSI Design Lecture 20 Power...

Info iconThis preview shows pages 1–4. Sign up to view the full content.

View Full Document Right Arrow Icon
1 ECE520 – Lecture 20 Slide: 1 University of New Mexico Office: ECE Bldg. 230B Office hours: Tuesday 2:00-3:00PM or by appointment E-mail: [email protected] Payman Zarkesh-Ha ECE520 – VLSI Design ECE520 – Lecture 20 Slide: 2 University of New Mexico Review of Last Lecture Clock Distribution Network Clock generation (PLLs) Clock distribution Clock gaters
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
2 ECE520 – Lecture 20 Slide: 3 University of New Mexico Today’s Lecture Power Distribution Network IR drop Switching noise Decoupling capacitor Electromigrartion I/O Circuits Output buffer Level shifters Schmitt trigger Tri-state outputs ESD protection ECE520 – Lecture 20 Slide: 4 University of New Mexico Power Distribution Network Purpose of Power Distribution Network Providing power supply and ground to every gate Maintaining stable supply voltage across the chip (noise<10%) Providing robust supply to entire chip (electromigration) Challenges in Power Distribution Network Design Carrying 100’s of amps with only 1 V power supply Stabilizing the power while millions of gates are switching simultaneously Via resistance and electromigration limit becomes bottleneck Power Distribution Design Consideration IR-drop consideration Switching noise limitation Wiring area requirement Electromigration
Background image of page 2
ECE520 – Lecture 20 Slide: 5 University of New Mexico Power Distribution Network Like clock distribution network, power distribution network consists of global and local networks Global power distribution network are routed at top metal levels across the chip with think and wide routes Local power distribution are within smaller blocks and connects all gates’ power/ground pins together ECE520 – Lecture 20 Slide: 6 University of New Mexico IR Drop Consideration On chip wiring resistance dominates IR drop IR drop affects the performance (increases delay). Why? Power distribution network must be designed carefully to meet IR drop noise limit. How? Modern chips devoted about 50% of wiring resource to power
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Image of page 4
This is the end of the preview. Sign up to access the rest of the document.

{[ snackBarMessage ]}

Page1 / 13

lecture20 - ECE520 VLSI Design Lecture 20 Power...

This preview shows document pages 1 - 4. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online