lecture21 - ECE520 VLSI Design Lecture 21: Memories Payman...

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1 ECE520 – Lecture 21 Slide: 1 University of New Mexico Office: ECE Bldg. 230B Office hours: Tuesday 2:00-3:00PM or by appointment E-mail: payman@ece.unm.edu Payman Zarkesh-Ha ECE520 – VLSI Design Lecture 21: Memories ECE520 – Lecture 21 Slide: 2 University of New Mexico Review of Last Lecture Power Distribution Network IR drop Switching noise Decoupling capacitor Electromigrartion I/O Circuits Output buffer Level shifters Schmitt trigger Tri-state outputs ESD protection
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2 ECE520 – Lecture 21 Slide: 3 University of New Mexico Today’s Lecture Memory architectures ROM NOR ROMs NAND ROMs ECE520 – Lecture 21 Slide: 4 University of New Mexico Types of VLSI Memories Register files Fastest and largest--sub 200ps access times possible Readily implemented with multiple ports SRAM Next fastest--sub 1ns access times possible This includes cache memory--they are all SRAM based Volatile, but retains state as long as power is applied DRAM Quite slow > 50ns access times Volatile--state retained for ms and must be refreshed often ROM Mask programmable Read Only Memory Non-volatile memories Slow--50ns access times EPROM, EEPROM, Flash Emerging technologies: Ferroelectric, ferromagnetic…
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3 ECE520 – Lecture 21 Slide: 5 University of New Mexico A Generic Memory Architecture Words are horizontal and accessed by applying the appropriate word line Each cell in a row is a bit in the corresponding word This is not practical. Why?
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lecture21 - ECE520 VLSI Design Lecture 21: Memories Payman...

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