lecture23 - ECE520 VLSI Design Lecture 23: SRAM & DRAM...

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1 ECE520 – Lecture 23 Slide: 1 University of New Mexico Office: ECE Bldg. 230B Office hours: Tuesday 2:00-3:00PM or by appointment E-mail: payman@ece.unm.edu Payman Zarkesh-Ha ECE520 – VLSI Design ECE520 – Lecture 23 Slide: 2 University of New Mexico Review of Last Lecture Nonvolatile Memories EPROM EEPROM Flash
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2 ECE520 – Lecture 23 Slide: 3 University of New Mexico Today’s Lecture Static Random-Access Memory (SRAM) SRAM cell SRAM architecture Sense amplifier Dynamic Random-Access Memory (DRAM) DRAM cells DRAM Capacitor implementation DRAM Sense amplifier ECE520 – Lecture 23 Slide: 4 University of New Mexico SRAM Cell SRAM cell is quite similar to flip-flop without any protective circuitry Therefore, reliable operation imposes transistor sizing constraints. Cell is selected by word line (WL=1) and read and write are often differential BL
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3 ECE520 – Lecture 23 Slide: 5 University of New Mexico 6-T SRAM Cell SRAM cell consists of 6 transistors (6T cell) with differential BL When reading, BLs are at VDD and have high capacitance This is essentially a short to VDD for both side of the cell The side at logic one is unaffected. e.g. Q at VDD and BL at VDD Node Q is pulled up by the voltage divider of two NMOS transistors WL BL V DD M 5 M 6 M 4 M 1 M 2 M 3 BL Q Q ECE520 – Lecture 23 Slide: 6 University of New Mexico 6-T SRAM Cell – Read operation The pull down must be stronger than the access transistor The access transistor is then generally narrower and longer channel Read margin is greatly affected by process variation The amount of voltage rise at Q node, Δ V is computed as follow: WL BL V DD M 5 M 6 M 4 M 1 V DD V DD V DD BL Q = 1 Q = 0 C bit C bit
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This note was uploaded on 01/11/2011 for the course ECE 520 taught by Professor Zarkesh-ha,p during the Fall '08 term at New Mexico.

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lecture23 - ECE520 VLSI Design Lecture 23: SRAM & DRAM...

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