hw5 - Homework five EECS 203 Due 8 May 2009 1. (10 pts.) A...

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Unformatted text preview: Homework five EECS 203 Due 8 May 2009 1. (10 pts.) A state machine is implemented with 3 flip-flops, and has a clock input, 4 data input wires and five output wires. The FSM could be implemented as either a Moore or a Mealy machine. (a) The maximum possible number of states in the machine is: (b) The minimum number of transition arrows starting at a given state is: (c) The minimum number of transition arrows terminating at a given state: (d) The number of unique patterns displayed at the output wires for a Moore machine is: (e) The number of unique patterns displayed at the output wires for a Mealy machine is: 2. (10 pts.) Number systems (a) Convert 0xBADF00D to binary. Note: This is easier if you convert it to base-16 one digit at a time instead of considering the whole number at once. (b) Convert (302)8 to base-10, and back again. (c) Convert 744 to base-7 and back again. 3. (10 pts.) When does overflow happen in unsigned adder-subtractor and two’s complement adder-subtractor and why? Use Boolean functions to express the overflow conditions. 4. (20 pts.) Suppose we have only one 8-bit ripple carry adder but need to do 16-bit addition and subtraction. Design a sequential circuit (FSM) with only one 8-bit ripple carry adder to implement a 16-bit adder-subtractor. You are allowed to use MUXs and need to generate the overflow signal. 1 ...
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