RequiresAcrobat6_IE

RequiresAcrobat6_IE - INTEGRATED CIRCUITS...

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: INTEGRATED CIRCUITS 89C51/89C52/89C54/89C58 80C51 8-bit microcontroller family 4K/8K/16K/32K Flash Product specification 1999 Oct 27 Replaces Datasheets 89C51 of 1999 Apr 01 and 89C52/89C54/89C58 of 1999 Apr 01 Philips Semiconductors Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4K/8K/16K/32K Flash 89C51/89C52/89C54/89C58 DESCRIPTION The 89C51/89C52/89C54/89C58 contain a non-volatile FLASH program memory that is parallel programmable. For devices that are serial programmable (In System Programmable (ISP) with a boot loader), see the 89C51RC+/89C51RD+ datasheet. Both families are Single-Chip 8-bit Microcontrollers manufactured in advanced CMOS process and are derivatives of the 80C51 microcontroller family. All the devices have the same instruction set as the 80C51. FEATURES SELECTION TABLE FOR FLASH DEVICES ROM/EPROM Memory Size (X by 8) RAM Size (X by 8) Programmable Timer Counter (PCA) Hardware Watchdog Timer • 80C51 Central Processing Unit • On-chip FLASH Program Memory • Speed up to 33 MHz • Full static operation • RAM expandable externally to 64 k bytes • 4 level priority interrupt • 6 interrupt sources • Four 8-bit I/O ports • Full-duplex enhanced UART – Framing error detection – Automatic address recognition Multi-Time Programmable (MTP) devices: 89C51 4k 89C52/54/58 8 k/16 k/32 k 89C51RC+ 32 k 89C51RD+ 64 k 1024 Yes Yes 512 Yes Yes 256 No No Serial In-System Programmable devices: 128 No No • Power control modes – Clock can be stopped and resumed – Idle mode – Power down mode • Programmable clock out • Second DPTR register • Asynchronous port reset • Low EMI (inhibit ALE) • 3 16-bit timers • Wake up from power down by an external interrupt ORDERING INFORMATION MEMORY SIZE 4k×8 FLASH FLASH FLASH FLASH FLASH FLASH P89C51UBA A P89C51UBP N P89C51UBB B P89C51UFA A P89C51UFP N P89C51UFB B MEMORY SIZE 8k×8 P89C52UBA A P89C52UBP N P89C52UBB B P89C52UFA A P89C52UFP N P89C52UFB B MEMORY SIZE 16 k × 8 P89C54UBA A P89C54UBP N P89C54UBB B P89C54UFA A P89C54UFP N P89C54UFB B MEMORY SIZE 32 k × 8 P89C58UBA A P89C58UBP N P89C58UBB B P89C58UFA A1 P89C58UFP N1 P89C58UFB B1 TEMPERATURE RANGE °C AND PACKAGE 0 to +70, Plastic Leaded Chip Carrier 0 to +70, Plastic Dual In-line Package 0 to +70, Plastic Quad Flat Pack –40 to +85, Plastic Leaded Chip Carrier –40 to +85, Plastic Dual In-line Package –40 to +85, Plastic Quad Flat Pack VOLTAGE RANGE 5V 5V 5V 5V 5V 5V FREQ. (MHz) 0 to 33 0 to 33 0 to 33 0 to 33 0 to 33 0 to 33 DWG. # SOT187-2 SOT129-1 QFP442 SOT187-2 SOT129-1 QFP442 NOTES: 1. Contact Philips Sales for availability. 2. SOT not assigned for this package outline. PART NUMBER DERIVATION DEVICE NUMBER (P89CXX) P89C51 FLASH P89C52 FLASH P89C54 FLASH P89C58 FLASH U = 33 MHz B = 0_C to 70_C F = –40_C to 85_C OPERATING FREQUENCY, MAX (V) TEMPERATURE RANGE (B) PACKAGE (AA, BB, PN) AA = PLCC BB = PQFP PN = PDIP 1999 Oct 27 2 853–2148 22592 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4K/8K/16K/32K Flash 89C51/89C52/89C54/89C58 BLOCK DIAGRAM P0.0–P0.7 P2.0–P2.7 PORT 0 DRIVERS VCC VSS RAM ADDR REGISTER RAM PORT 0 LATCH PORT 2 DRIVERS PORT 2 LATCH FLASH 8 B REGISTER STACK POINTER ACC TMP2 TMP1 PROGRAM ADDRESS REGISTER ALU BUFFER SFRs PSW TIMERS PC INCREMENTER 8 PROGRAM COUNTER PSEN ALE EAVPP RST PD TIMING AND CONTROL INSTRUCTION REGISTER 16 DPTR’S MULTIPLE PORT 1 LATCH PORT 3 LATCH OSCILLATOR PORT 1 DRIVERS XTAL1 XTAL2 P1.0–P1.7 PORT 3 DRIVERS P3.0–P3.7 SU01066 1999 Oct 27 3 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4K/8K/16K/32K Flash 89C51/89C52/89C54/89C58 LOGIC SYMBOL VCC XTAL1 PORT 0 ADDRESS AND DATA BUS VSS Ceramic and Plastic Leaded Chip Carrier Pin Functions 6 1 40 7 39 LCC XTAL2 T2 T2EX RST EA/VPP PSEN SECONDARY FUNCTIONS ALE/PROG RxD TxD INT0 INT1 T0 T1 WR RD PORT 1 17 29 18 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Function NIC* P1.0/T2 P1.1/T2EX P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST P3.0/RxD NIC* P3.1/TxD P3.2/INT0 P3.3/INT1 Pin 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Function P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1 VSS NIC* P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 28 Pin 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Function P2.7/A15 PSEN ALE NIC* EA/VPP P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VCC PORT 3 PORT 2 ADDRESS BUS SU00830 PIN CONFIGURATIONS Dual In-Line Package Pin Functions T2/P1.0 1 T2EX/P1.1 2 P1.2 3 P1.3 4 P1.4 5 P1.5 6 P1.6 7 P1.7 8 RST 9 RxD/P3.0 10 TxD/P3.1 11 INT0/P3.2 12 INT1/P3.3 13 T0/P3.4 14 T1/P3.5 15 WR/P3.6 16 RD/P3.7 17 XTAL2 18 XTAL1 19 VSS 20 DUAL IN-LINE PACKAGE 40 VCC 39 P0.0/AD0 38 P0.1/AD1 37 P0.2/AD2 36 P0.3/AD3 35 P0.4/AD4 34 P0.5/AD5 33 P0.6/AD6 * NO INTERNAL CONNECTION SU01062 Plastic Quad Flat Pack Pin Functions 44 34 1 33 PQFP 11 32 P0.7/AD7 31 EA/VPP 30 ALE 29 PSEN 28 P2.7/A15 27 P2.6/A14 26 P2.5/A13 25 P2.4/A12 24 P2.3/A11 23 P2.2/A10 22 P2.1/A9 21 P2.0/A8 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Function P1.5 P1.6 P1.7 RST P3.0/RxD NIC* P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1 12 Pin 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Function VSS NIC* P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 PSEN ALE NIC* EA/VPP P0.7/AD7 22 23 Pin 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Function P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VCC NIC* P1.0/T2 P1.1/T2EX P1.2 P1.3 P1.4 SU01063 * NO INTERNAL CONNECTION SU01064 1999 Oct 27 4 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4K/8K/16K/32K Flash 89C51/89C52/89C54/89C58 PIN DESCRIPTIONS PIN NUMBER MNEMONIC VSS VCC P0.0–0.7 DIP 20 40 39–32 LCC 22 44 43–36 QFP 16 38 37–30 TYPE I I I/O NAME AND FUNCTION Ground: 0 V reference. Power Supply: This is the power supply voltage for normal, idle, and power-down operation. Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application, it uses strong internal pull-ups when emitting 1s. Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Alternate function for Port 1: T2 (P1.0): Timer/Counter2 external count input/clockout (see Programmable Clock-Out). T2EX (P1.1): Timer/Counter2 reload/capture/direction control. Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 2 pins that are externally being pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function register. Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (See DC Electrical Characteristics: IIL). Port 3 also serves the special features of the 89C51/89C52/89C54/89C58, as listed below: RxD (P3.0): Serial input port TxD (P3.1): Serial output port INT0 (P3.2): External interrupt INT1 (P3.3): External interrupt T0 (P3.4): Timer 0 external input T1 (P3.5): Timer 1 external input WR (P3.6): External data memory write strobe RD (P3.7): External data memory read strobe Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to VCC. Address Latch Enable: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. ALE can be disabled by setting SFR auxiliary.0. With this bit set, ALE will be active only during a MOVX instruction. Program Store Enable: The read strobe to external program memory. When executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. External Access Enable/Programming Supply Voltage: EA must be externally held low to enable the device to fetch code from external program memory locations 0000H to the maximum internal memory boundary. If EA is held high, the device executes from internal program memory unless the program counter contains an address greater than 0FFFH for 4 k devices, 1FFFH for 8 k devices, 3FFFH for 16 k devices, and 7FFFH for 32 k devices. The value on the EA pin is latched when RST is released and any subsequent changes have no effect. This pin also receives the 12.00 V programming supply voltage (VPP) during FLASH programming. Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. Crystal 2: Output from the inverting oscillator amplifier. P1.0–P1.7 1–8 2–9 40–44, 1–3 I/O 1 2 P2.0–P2.7 21–28 2 3 24–31 40 41 18–25 I/O I I/O P3.0–P3.7 10–17 11, 13–19 5, 7–13 I/O 10 11 12 13 14 15 16 17 RST 9 11 13 14 15 16 17 18 19 10 5 7 8 9 10 11 12 13 4 I O I I I I O O I ALE 30 33 27 O PSEN 29 32 26 O EA/VPP 31 35 29 I XTAL1 XTAL2 19 18 21 20 15 14 I O NOTE: To avoid “latch-up” effect at power-on, the voltage on any pin (other than VPP) at any time must not be higher than VCC + 0.5 V or VSS – 0.5 V, respectively. 1999 Oct 27 5 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4K/8K/16K/32K Flash 89C51/89C52/89C54/89C58 Table 1. SYMBOL ACC* AUXR# AUXR1# B* DPTR: DPH DPL IE* IP* IPH# P0* P1* P2* P3* PCON#1 PSW* RACAP2H# RACAP2L# SADDR# SADEN# SBUF SCON* SP TCON* T2CON* T2MOD# TH0 TH1 TH2# TL0 TL1 TL2# TMOD * # – 1. 2. 89C51/89C52/89C54/89C58 Special Function Registers DESCRIPTION Accumulator Auxiliary Auxiliary 1 B register Data Pointer (2 bytes) Data Pointer High Data Pointer Low Interrupt Enable Interrupt Priority Interrupt Priority High Port 0 Port 1 Port 2 Port 3 Power Control Program Status Word Timer 2 Capture High Timer 2 Capture Low Slave Address Slave Address Mask Serial Data Buffer Serial Control Stack Pointer Timer Control Timer 2 Control Timer 2 Mode Control Timer High 0 Timer High 1 Timer High 2 Timer Low 0 Timer Low 1 Timer Low 2 Timer Mode DIRECT ADDRESS E0H 8EH A2H F0H 83H 82H AF A8H B8H B7H 80H 90H A0H B0H 87H D0H CBH CAH A9H B9H 99H 9F 98H 81H 8F 88H C8H C9H 8CH 8DH CDH 8AH 8BH CCH 89H TF1 CF TF2 – 8E TR1 CE EXF2 – 8D TF0 CD RCLK – 8C TR0 CC TCLK – 8B IE1 CB EXEN2 – 8A IT1 CA TR2 – 89 IE0 C9 C/T2 T2OE 88 IT0 C8 CP/RL2 DCEN 00H xxxxxx00B 00H 00H 00H 00H 00H 00H 00H 00H SM0/FE BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION MSB E7 – – F7 E6 – – F6 E5 – – F5 E4 – – F4 E3 – GF2 F3 E2 – 0 F2 E1 – – F1 LSB E0 AO DPS F0 RESET VALUE 00H xxxxxxx0B xxxx00x0B 00H 00H 00H AE – BE – B6 – 86 AD6 96 – A6 AD14 B6 WR SMOD0 D6 AC AD ET2 BD PT2 B5 PT2H 85 AD5 95 – A5 AD13 B5 T1 – D5 F0 AC ES BC PS B4 PSH 84 AD4 94 – A4 AD12 B4 T0 POF2 D4 RS1 AB ET1 BB PT1 B3 PT1H 83 AD3 93 – A3 AD11 B3 INT1 GF1 D3 RS0 AA EX1 BA PX1 B2 PX1H 82 AD2 92 – A2 AD10 B2 INT0 GF0 D2 OV A9 ET0 B9 PT0 B1 PT0H 81 AD1 91 T2EX A1 AD9 B1 TxD PD D1 – A8 EX0 B8 PX0 B0 PX0H 80 AD0 90 T2 A0 AD8 B0 RxD IDL D0 P 000000x0B 00H 00H 00H 00H xxxxxxxxB FFH 00xxx000B FFH FFH FFH xx000000B xx000000B 0x000000B EA BF – B7 – 87 AD7 97 – A7 AD15 B7 RD SMOD1 D7 CY 9E SM1 9D SM2 9C REN 9B TB8 9A RB8 99 TI 98 RI 00H 07H GATE C/T M1 M0 GATE C/T M1 M0 SFRs are bit addressable. SFRs are modified from or added to the 80C51 SFRs. Reserved bits. Reset value depends on reset source. Bit will not be affected by reset. 6 1999 Oct 27 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4K/8K/16K/32K Flash 89C51/89C52/89C54/89C58 FLASH EPROM MEMORY General Description The 89C51/89C52/89C54/89C58 FLASH reliably stores memory contents even after 100 erase and program cycles. The cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. OSCILLATOR CHARACTERISTICS XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier. The pins can be configured for use as an on-chip oscillator. To drive the device from an external clock source, XTAL1 should be driven while XTAL2 is left unconnected. There are no requirements on the duty cycle of the external clock signal, because the input to the internal clock circuitry is through a divide-by-two flip-flop. However, minimum and maximum high and low times specified in the data sheet must be observed. Features • FLASH EPROM internal program memory with Chip Erase • Up to 64 k byte external program memory if the internal program memory is disabled (EA = 0) RESET A reset is accomplished by holding the RST pin high for at least two machine cycles (24 oscillator periods), while the oscillator is running. To insure a good power-on reset, the RST pin must be high long enough to allow the oscillator time to start up (normally a few milliseconds) plus two machine cycles. At power-on, the voltage on VCC and RST must come up at the same time for a proper start-up. Ports 1, 2, and 3 will asynchronously be driven to their reset condition when a voltage above VIH1 (min.) is applied to RESET. The value on the EA pin is latched when RST is deasserted and has no further effect. • Programmable security bits • 100 minimum erase/program cycles for each byte • 10 year minimum data retention • Programming support available from many popular vendors 1999 Oct 27 7 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4K/8K/16K/32K Flash 89C51/89C52/89C54/89C58 LOW POWER MODES Stop Clock Mode The static design enables the clock speed to be reduced down to 0 MHz (stopped). When the oscillator is stopped, the RAM and Special Function Registers retain their values. This mode allows step-by-step utilization and permits reduced system power consumption by lowering the clock frequency down to any value. For lowest power consumption the Power Down mode is suggested. Design Consideration • When the idle mode is terminated by a hardware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory. Idle Mode In the idle mode (see Table 2), the CPU puts itself to sleep while all of the on-chip peripherals stay active. The instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the idle mode is activated. The CPU contents, the on-chip RAM, and all of the special function registers remain intact during this mode. The idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt service routine and continued), or by a hardware reset which starts the processor in the same manner as a power-on reset. ONCE™ Mode The ONCE (“On-Circuit Emulation”) Mode facilitates testing and debugging of systems without the device having to be removed from the circuit. The ONCE Mode is invoked by: 1. Pull ALE low while the device is in reset and PSEN is high; 2. Hold ALE low as RST is deactivated. While the device is in ONCE Mode, the Port 0 pins go into a float state, and the other port pins and ALE and PSEN are weakly pulled high. The oscillator circuit remains active. While the device is in this mode, an emulator or test CPU can be used to drive the circuit. Normal operation is restored when a normal reset is applied. Power-Down Mode To save even more power, a Power Down mode (see Table 2) can be invoked by software. In this mode, the oscillator is stopped and the instruction that invoked Power Down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values down to 2.0 V and care must be taken to return VCC to the minimum specified operating voltages before the Power Down Mode is terminated. Either a hardware reset or external interrupt can be used to exit from Power Down. Reset redefines all the SFRs but does not change the on-chip RAM. An external interrupt allows both the SFRs and the on-chip RAM to retain their values. To properly terminate Power Down the reset or external interrupt should not be executed before VCC is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize (normally less than 10ms). With an external interrupt, INT0 and INT1 must be enabled and configured as level-sensitive. Holding the pin low restarts the oscillator but bringing the pin back high completes the exit. Once the interrupt is serviced, the next instruction to be executed after RETI will be the one following the instruction that put the device into Power Down. Programmable Clock-Out A 50% duty cycle clock can be programmed to come out on P1.0. This pin, besides being a regular I/O pin, has two alternate functions. It can be programmed: 1. to input the external clock for Timer/Counter 2, or 2. to output a 50% duty cycle clock ranging from 61Hz to 4MHz at a 16MHz operating frequency. To configure the Timer/Counter 2 as a clock generator, bit C/T2 (in T2CON) must be cleared and bit T20E in T2MOD must be set. Bit TR2 (T2CON.2) also must be set to start the timer. The Clock-Out frequency depends on the oscillator frequency and the reload value of Timer 2 capture registers (RCAP2H, RCAP2L) as shown in this equation: 4 Oscillator Frequency (65536 * RCAP2H, RCAP2L) Where (RCAP2H,RCAP2L) = the content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer. In the Clock-Out mode Timer 2 roll-overs will not generate an interrupt. This is similar to when it is used as a baud-rate generator. It is possible to use Timer 2 as a baud-rate generator and a clock generator simultaneously. Note, however, that the baud-rate and the Clock-Out frequency will be the same. Table 2. MODE Idle Idle External Pin Status During Idle and Power-Down Mode PROGRAM MEMORY Internal External Internal External ALE 1 1 0 0 PSEN 1 1 0 0 PORT 0 Data Float Data Float PORT 1 Data Data Data Data PORT 2 Data Address Data Data PORT 3 Data Data Data Data Power-down Power-down 1999 Oct 27 8 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4K/8K/16K/32K Flash 89C51/89C52/89C54/89C58 TIMER 2 OPERATION Timer 2 Timer 2 is a 16-bit Timer/Counter which can operate as either an event timer or an event counter, as selected by C/T2* in the special function register T2CON (see Figure 1). Timer 2 has three operating modes: Capture, Auto-reload (up or down counting), and Baud Rate Generator, which are selected by bits in the T2CON as shown in Table 3. Figure 3). When reset is applied the DCEN=0 which means Timer 2 will default to counting up. If DCEN bit is set, Timer 2 can count up or down depending on the value of the T2EX pin. Figure 4 shows Timer 2 which will count up automatically since DCEN=0. In this mode there are two options selected by bit EXEN2 in T2CON register. If EXEN2=0, then Timer 2 counts up to 0FFFFH and sets the TF2 (Overflow Flag) bit upon overflow. This causes the Timer 2 registers to be reloaded with the 16-bit value in RCAP2L and RCAP2H. The values in RCAP2L and RCAP2H are preset by software means. If EXEN2=1, then a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at input T2EX. This transition also sets the EXF2 bit. The Timer 2 interrupt, if enabled, can be generated when either TF2 or EXF2 are 1. In Figure 5 DCEN=1 which enables Timer 2 to count up or down. This mode allows pin T2EX to control the direction of count. When a logic 1 is applied at pin T2EX Timer 2 will count up. Timer 2 will overflow at 0FFFFH and set the TF2 flag, which can then generate an interrupt, if the interrupt is enabled. This timer overflow also causes the 16–bit value in RCAP2L and RCAP2H to be reloaded into the timer registers TL2 and TH2. When a logic 0 is applied at pin T2EX this causes Timer 2 to count down. The timer will underflow when TL2 and TH2 become equal to the value stored in RCAP2L and RCAP2H. Timer 2 underflow sets the TF2 flag and causes 0FFFFH to be reloaded into the timer registers TL2 and TH2. The external flag EXF2 toggles when Timer 2 underflows or overflows. This EXF2 bit can be used as a 17th bit of resolution if needed. The EXF2 flag does not generate an interrupt in this mode of operation. Capture Mode In the capture mode there are two options which are selected by bit EXEN2 in T2CON. If EXEN2=0, then timer 2 is a 16-bit timer or counter (as selected by C/T2* in T2CON) which, upon overflowing sets bit TF2, the timer 2 overflow bit. This bit can be used to generate an interrupt (by enabling the Timer 2 interrupt bit in the IE register). If EXEN2= 1, Timer 2 operates as described above, but with the added feature that a 1- to -0 transition at external input T2EX causes the current value in the Timer 2 registers, TL2 and TH2, to be captured into registers RCAP2L and RCAP2H, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set, and EXF2 like TF2 can generate an interrupt (which vectors to the same location as Timer 2 overflow interrupt. The Timer 2 interrupt service routine can interrogate TF2 and EXF2 to determine which event caused the interrupt). The capture mode is illustrated in Figure 2 (There is no reload value for TL2 and TH2 in this mode. Even when a capture event occurs from T2EX, the counter keeps on counting T2EX pin transitions or osc/12 pulses.). Auto-Reload Mode (Up or Down Counter) In the 16-bit auto-reload mode, Timer 2 can be configured (as either a timer or counter [C/T2* in T2CON]) then programmed to count up or down. The counting direction is determined by bit DCEN (Down Counter Enable) which is located in the T2MOD register (see (MSB) TF2 Symbol TF2 EXF2 Position T2CON.7 T2CON.6 EXF2 RCLK TCLK EXEN2 TR2 C/T2 (LSB) CP/RL2 Name and Significance Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either RCLK or TCLK = 1. Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1). Receive clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock. Transmit clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock. Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX. Start/stop control for Timer 2. A logic 1 starts the timer. Timer or counter select. (Timer 2) 0 = Internal timer (OSC/12) 1 = External event counter (falling edge triggered). Capture/Reload flag. When set, captures will occur on negative transitions at T2EX if EXEN2 = 1. When cleared, auto-reloads will occur either with Timer 2 overflows or negative transitions at T2EX when EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow. SU00728 RCLK TCLK EXEN2 T2CON.5 T2CON.4 T2CON.3 TR2 C/T2 T2CON.2 T2CON.1 CP/RL2 T2CON.0 Figure 1. Timer/Counter 2 (T2CON) Control Register 1999 Oct 27 9 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4K/8K/16K/32K Flash 89C51/89C52/89C54/89C58 Table 3. Timer 2 Operating Modes CP/RL2 0 1 X X TR2 1 1 1 0 16-bit Auto-reload 16-bit Capture Baud rate generator (off) MODE 0 0 1 X RCLK + TCLK OSC ÷ 12 C/T2 = 0 TL2 (8-bits) C/T2 = 1 TH2 (8-bits) TF2 T2 Pin Control TR2 Transition Detector Capture Timer 2 Interrupt RCAP2L RCAP2H T2EX Pin EXF2 Control EXEN2 SU00066 Figure 2. Timer 2 in Capture Mode T2MOD Address = 0C9H Not Bit Addressable — Bit 7 — 6 — 5 — 4 — 3 — 2 T2OE 1 Reset Value = XXXX XX00B DCEN 0 Symbol — T2OE DCEN * Function Not implemented, reserved for future use.* Timer 2 Output Enable bit. Down Count Enable bit. When set, this allows Timer 2 to be configured as an up/down counter. User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. Figure 3. Timer 2 Mode (T2MOD) Control Register SU00729 1999 Oct 27 10 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4K/8K/16K/32K Flash 89C51/89C52/89C54/89C58 OSC ÷ 12 C/T2 = 0 TL2 (8-BITS) C/T2 = 1 TH2 (8-BITS) T2 PIN CONTROL TR2 RELOAD TRANSITION DETECTOR RCAP2L RCAP2H TF2 TIMER 2 INTERRUPT T2EX PIN EXF2 CONTROL EXEN2 SU00067 Figure 4. Timer 2 in Auto-Reload Mode (DCEN = 0) (DOWN COUNTING RELOAD VALUE) FFH FFH TOGGLE EXF2 OSC ÷12 C/T2 = 0 OVERFLOW TL2 TH2 TF2 INTERRUPT T2 PIN C/T2 = 1 CONTROL TR2 COUNT DIRECTION 1 = UP 0 = DOWN RCAP2L RCAP2H T2EX PIN (UP COUNTING RELOAD VALUE) SU00730 Figure 5. Timer 2 Auto Reload Mode (DCEN = 1) 1999 Oct 27 11 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4K/8K/16K/32K Flash 89C51/89C52/89C54/89C58 Timer 1 Overflow NOTE: OSC. Freq. is divided by 2, not 12. ÷2 C/T2 = 0 TL2 (8-bits) C/T2 = 1 T2 Pin Control TH2 (8-bits) “1” ÷2 “0” “1” SMOD “0” RCLK OSC ÷ 16 TR2 “1” Reload “0” RX Clock TCLK Transition Detector RCAP2L RCAP2H ÷ 16 TX Clock T2EX Pin EXF2 Timer 2 Interrupt Control EXEN2 Note availability of additional external interrupt. SU00068 Figure 6. Timer 2 in Baud Rate Generator Mode Table 4. Timer 2 Generated Commonly Used Baud Rates Timer 2 Osc Freq Freq 12 MHz 12 MHz 12 MHz 12 MHz 12 MHz 12 MHz 12 MHz 6 MHz 6 MHz RCAP2H FF FF FF FF FE FB F2 FD F9 RCAP2L FF D9 B2 64 C8 1E AF 8F 57 The baud rates in modes 1 and 3 are determined by Timer 2’s overflow rate given below: Modes 1 and 3 Baud Rates + Timer 2 Overflow Rate 16 The timer can be configured for either “timer” or “counter” operation. In many applications, it is configured for “timer” operation (C/T2*=0). Timer operation is different for Timer 2 when it is being used as a baud rate generator. Usually, as a timer it would increment every machine cycle (i.e., 1/12 the oscillator frequency). As a baud rate generator, it increments every state time (i.e., 1/2 the oscillator frequency). Thus the baud rate formula is as follows: Modes 1 and 3 Baud Rates = Oscillator Frequency [32 [65536 * (RCAP2H, RCAP2L)]] Where: (RCAP2H, RCAP2L) = The content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer. The Timer 2 as a baud rate generator mode shown in Figure 6, is valid only if RCLK and/or TCLK = 1 in T2CON register. Note that a rollover in TH2 does not set TF2, and will not generate an interrupt. Thus, the Timer 2 interrupt does not have to be disabled when Timer 2 is in the baud rate generator mode. Also if the EXEN2 (T2 external enable flag) is set, a 1-to-0 transition in T2EX (Timer/counter 2 trigger input) will set EXF2 (T2 external flag) but will not cause a reload from (RCAP2H, RCAP2L) to (TH2,TL2). Therefore when Timer 2 is in use as a baud rate generator, T2EX can be used as an additional external interrupt, if needed. Baud Rate Rate 375 k 9.6 k 2.8 k 2.4 k 1.2 k 300 110 300 110 Baud Rate Generator Mode Bits TCLK and/or RCLK in T2CON (Table 4) allow the serial port transmit and receive baud rates to be derived from either Timer 1 or Timer 2. When TCLK= 0, Timer 1 is used as the serial port transmit baud rate generator. When TCLK= 1, Timer 2 is used as the serial port transmit baud rate generator. RCLK has the same effect for the serial port receive baud rate. With these two bits, the serial port can have different receive and transmit baud rates – one generated by Timer 1, the other by Timer 2. Figure 6 shows the Timer 2 in baud rate generation mode. The baud rate generation mode is like the auto-reload mode, in that a rollover in TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and RCAP2L, which are preset by software. 1999 Oct 27 12 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4K/8K/16K/32K Flash 89C51/89C52/89C54/89C58 When Timer 2 is in the baud rate generator mode, one should not try to read or write TH2 and TL2. As a baud rate generator, Timer 2 is incremented every state time (osc/2) or asynchronously from pin T2; under these conditions, a read or write of TH2 or TL2 may not be accurate. The RCAP2 registers may be read, but should not be written to, because a write might overlap a reload and cause write and/or reload errors. The timer should be turned off (clear TR2) before accessing the Timer 2 or RCAP2 registers. Table 4 shows commonly used baud rates and how they can be obtained from Timer 2. If Timer 2 is being clocked internally , the baud rate is: Baud Rate + f OSC [65536 * (RCAP2H, RCAP2L)]] [32 Where fOSC= Oscillator Frequency To obtain the reload value for RCAP2H and RCAP2L, the above equation can be rewritten as: RCAP2H, RCAP2L + 65536 * f OSC Baud Rate 32 Summary Of Baud Rate Equations Timer 2 is in baud rate generating mode. If Timer 2 is being clocked through pin T2(P1.0) the baud rate is: Baud Rate + Timer 2 Overflow Rate 16 Timer/Counter 2 Set-up Except for the baud rate generator mode, the values given for T2CON do not include the setting of the TR2 bit. Therefore, bit TR2 must be set, separately, to turn the timer on. see Table 5 for set-up of Timer 2 as a timer. Also see Table 6 for set-up of Timer 2 as a counter. Table 5. Timer 2 as a Timer T2CON MODE INTERNAL CONTROL (Note 1) 00H 01H 34H 24H 14H EXTERNAL CONTROL (Note 2) 08H 09H 36H 26H 16H 16-bit Auto-Reload 16-bit Capture Baud rate generator receive and transmit same baud rate Receive only Transmit only Table 6. Timer 2 as a Counter TMOD MODE INTERNAL CONTROL (Note 1) 02H 03H EXTERNAL CONTROL (Note 2) 0AH 0BH 16-bit Auto-Reload NOTES: 1. Capture/reload occurs only on timer/counter overflow. 2. Capture/reload occurs on timer/counter overflow and a 1-to-0 transition on T2EX (P1.1) pin except when Timer 2 is used in the baud rate generator mode. 1999 Oct 27 13 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4K/8K/16K/32K Flash 89C51/89C52/89C54/89C58 Enhanced UART The UART operates in all of the usual modes that are described in the first section of Data Handbook IC20, 80C51-Based 8-Bit Microcontrollers. In addition the UART can perform framing error detect by looking for missing stop bits, and automatic address recognition. The UART also fully supports multiprocessor communication as does the standard 80C51 UART. When used for framing error detect the UART looks for missing stop bits in the communication. A missing bit will set the FE bit in the SCON register. The FE bit shares the SCON.7 bit with SM0 and the function of SCON.7 is determined by PCON.6 (SMOD0) (see Figure 7). If SMOD0 is set then SCON.7 functions as FE. SCON.7 functions as SM0 when SMOD0 is cleared. When used as FE SCON.7 can only be cleared by software. Refer to Figure 8. Automatic Address Recognition Automatic Address Recognition is a feature which allows the UART to recognize certain addresses in the serial bit stream by using hardware to make the comparisons. This feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port. This feature is enabled by setting the SM2 bit in SCON. In the 9 bit UART modes, mode 2 and mode 3, the Receive Interrupt flag (RI) will be automatically set when the received byte contains either the “Given” address or the “Broadcast” address. The 9 bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data. Automatic address recognition is shown in Figure 9. The 8 bit mode is called Mode 1. In this mode the RI flag will be set if SM2 is enabled and the information received has a valid stop bit following the 8 address bits and the information is either a Given or Broadcast address. Mode 0 is the Shift Register mode and SM2 is ignored. Using the Automatic Address Recognition feature allows a master to selectively communicate with one or more slaves by invoking the Given slave address or addresses. All of the slaves may be contacted by using the Broadcast address. Two special Function Registers are used to define the slave’s address, SADDR, and the address mask, SADEN. SADEN is used to define which bits in the SADDR are to b used and which bits are “don’t care”. The SADEN mask can be logically ANDed with the SADDR to create the “Given” address which the master will use for addressing each of the slaves. Use of the Given address allows multiple slaves to be recognized while excluding others. The following examples will help to show the versatility of this scheme: Slave 0 SADDR = SADEN = Given = 1100 0000 1111 1101 1100 00X0 Slave 1 SADDR = SADEN = Given = 1100 0000 1111 1110 1100 000X In the above example SADDR is the same and the SADEN data is used to differentiate between the two slaves. Slave 0 requires a 0 in bit 0 and it ignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0 is ignored. A unique address for Slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1. A unique address for slave 1 would be 1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can be selected at the same time by an address which has bit 0 = 0 (for slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed with 1100 0000. In a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0: Slave 0 SADDR = SADEN = Given = SADDR = SADEN = Given = SADDR = SADEN = Given = 1100 0000 1111 1001 1100 0XX0 1110 0000 1111 1010 1110 0X0X 1110 0000 1111 1100 1110 00XX Slave 1 Slave 2 In the above example the differentiation among the 3 slaves is in the lower 3 address bits. Slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = 0 and it can be uniquely addressed by 1110 and 0101. Slave 2 requires that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0 and 1 and exclude Slave 2 use address 1110 0100, since it is necessary to make bit 2 = 1 to exclude slave 2. The Broadcast Address for each slave is created by taking the logical OR of SADDR and SADEN. Zeros in this result are trended as don’t-cares. In most cases, interpreting the don’t-cares as ones, the broadcast address will be FF hexadecimal. Upon reset SADDR (SFR address 0A9H) and SADEN (SFR address 0B9H) are leaded with 0s. This produces a given address of all “don’t cares” as well as a Broadcast address of all “don’t cares”. This effectively disables the Automatic Addressing mode and allows the microcontroller to use standard 80C51 type UART drivers which do not make use of this feature. 1999 Oct 27 14 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4K/8K/16K/32K Flash 89C51/89C52/89C54/89C58 SCON Address = 98H Bit Addressable SM0/FE Bit: SM1 SM2 5 REN 4 TB8 3 RB8 2 Tl 1 Rl 0 Reset Value = 0000 0000B 7 6 (SMOD0 = 0/1)* Symbol FE SM0 SM1 Function Framing Error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not cleared by valid frames but should be cleared by software. The SMOD0 bit must be set to enable access to the FE bit. Serial Port Mode Bit 0, (SMOD0 must = 0 to access bit SM0) Serial Port Mode Bit 1 SM0 SM1 Mode 0 0 1 1 0 1 0 1 0 1 2 3 Description shift register 8-bit UART 9-bit UART 9-bit UART Baud Rate** fOSC/12 variable fOSC/64 or fOSC/32 variable SM2 Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then Rl will not be set unless the received 9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address. In Mode 1, if SM2 = 1 then Rl will not be activated unless a valid stop bit was received, and the received byte is a Given or Broadcast Address. In Mode 0, SM2 should be 0. Enables serial reception. Set by software to enable reception. Clear by software to disable reception. The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired. In modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received. In Mode 0, RB8 is not used. Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission. Must be cleared by software. Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the other modes, in any serial reception (except see SM2). Must be cleared by software. REN TB8 RB8 Tl Rl NOTE: *SMOD0 is located at PCON6. **fOSC = oscillator frequency SU00043 Figure 7. SCON: Serial Port Control Register 1999 Oct 27 15 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4K/8K/16K/32K Flash 89C51/89C52/89C54/89C58 D0 D1 D2 D3 D4 D5 D6 D7 D8 START BIT DATA BYTE ONLY IN MODE 2, 3 STOP BIT SET FE BIT IF STOP BIT IS 0 (FRAMING ERROR) SM0 TO UART MODE CONTROL SM0 / FE SM1 SM2 REN TB8 RB8 TI RI SCON (98H) SMOD1 SMOD0 – POF GF1 GF0 PD IDL PCON (87H) 0 : SCON.7 = SM0 1 : SCON.7 = FE SU01191 Figure 8. UART Framing Error Detection D0 D1 D2 D3 D4 D5 D6 D7 D8 SM0 1 1 SM1 1 0 SM2 1 REN 1 TB8 X RB8 TI RI SCON (98H) RECEIVED ADDRESS D0 TO D7 PROGRAMMED ADDRESS COMPARATOR IN UART MODE 2 OR MODE 3 AND SM2 = 1: INTERRUPT IF REN=1, RB8=1 AND “RECEIVED ADDRESS” = “PROGRAMMED ADDRESS” – WHEN OWN ADDRESS RECEIVED, CLEAR SM2 TO RECEIVE DATA BYTES – WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2 TO WAIT FOR NEXT ADDRESS. SU00045 Figure 9. UART Multiprocessor Communication, Automatic Address Recognition 1999 Oct 27 16 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4K/8K/16K/32K Flash 89C51/89C52/89C54/89C58 Interrupt Priority Structure The 89C51/89C52/89C54/89C58 have a 6-source four-level interrupt structure. There are 3 SFRs associated with the four-level interrupt. They are the IE, IP, and IPH. (See Figures 10, 11, and 12.) The IPH (Interrupt Priority High) register makes the four-level interrupt structure possible. The IPH is located at SFR address B7H. The structure of the IPH register and a description of its bits is shown in Figure 12. The function of the IPH SFR is simple and when combined with the IP SFR determines the priority of each interrupt. The priority of each interrupt is determined as shown in the following table: PRIORITY BITS IPH.x 0 0 1 1 IP.x 0 1 0 1 INTERRUPT PRIORITY LEVEL PRIORITY LEVEL Level 0 (lowest priority) Level 1 Level 2 Level 3 (highest priority) There are four interrupt levels rather than two as on the 80C51. An interrupt will be serviced as long as an interrupt of equal or higher priority is not already being serviced. If an interrupt of equal or higher level priority is being serviced, the new interrupt will wait until it is finished before being serviced. If a lower priority level interrupt is being serviced, it will be stopped and the new interrupt serviced. When the new interrupt is finished, the lower priority level interrupt that was stopped will be completed. Table 7. Interrupt Table POLLING PRIORITY 1 2 3 4 5 6 REQUEST BITS IE0 TP0 IE1 TF1 RI, TI TF2, EXF2 HARDWARE CLEAR? N (L)1 Y N (L) Y (T) Y N N Y (T)2 VECTOR ADDRESS 03H 0BH 13H 1BH 23H 2BH X0 T0 X1 T1 SP T2 SOURCE NOTES: 1. L = Level activated 2. T = Transition activated 7 IE (0A8H) EA 6 — 5 ET2 4 ES 3 ET1 2 EX1 1 ET0 0 EX0 Enable Bit = 1 enables the interrupt. Enable Bit = 0 disables it. BIT IE.7 IE.6 IE.5 IE.4 IE.3 IE.2 IE.1 IE.0 SYMBOL EA — ET2 ES ET1 EX1 ET0 EX0 FUNCTION Global disable bit. If EA = 0, all interrupts are disabled. If EA = 1, each interrupt can be individually enabled or disabled by setting or clearing its enable bit. Not implemented. Reserved for future use. Timer 2 interrupt enable bit. Serial Port interrupt enable bit. Timer 1 interrupt enable bit. External interrupt 1 enable bit. Timer 0 interrupt enable bit. External interrupt 0 enable bit. SU00571 Figure 10. IE Registers 1999 Oct 27 17 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4K/8K/16K/32K Flash 89C51/89C52/89C54/89C58 7 IP (0B8H) — 6 — 5 PT2 4 PS 3 PT1 2 PX1 1 PT0 0 PX0 Priority Bit = 1 assigns higher priority Priority Bit = 0 assigns lower priority BIT IP.7 IP.6 IP.5 IP.4 IP.3 IP.2 IP.1 IP.0 SYMBOL — — PT2 PS PT1 PX1 PT0 PX0 FUNCTION Not implemented, reserved for future use. Not implemented, reserved for future use. Timer 2 interrupt priority bit. Serial Port interrupt priority bit. Timer 1 interrupt priority bit. External interrupt 1 priority bit. Timer 0 interrupt priority bit. External interrupt 0 priority bit. Figure 11. IP Registers SU00572 7 IPH (B7H) — 6 — 5 PT2H 4 PSH 3 PT1H 2 PX1H 1 PT0H 0 PX0H Priority Bit = 1 assigns higher priority Priority Bit = 0 assigns lower priority BIT IPH.7 IPH.6 IPH.5 IPH.4 IPH.3 IPH.2 IPH.1 IPH.0 SYMBOL — — PT2H PSH PT1H PX1H PT0H PX0H FUNCTION Not implemented, reserved for future use. Not implemented, reserved for future use. Timer 2 interrupt priority bit high. Serial Port interrupt priority bit high. Timer 1 interrupt priority bit high. External interrupt 1 priority bit high. Timer 0 interrupt priority bit high. External interrupt 0 priority bit high. Figure 12. IPH Registers SU01058 1999 Oct 27 18 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4K/8K/16K/32K Flash 89C51/89C52/89C54/89C58 Reduced EMI Mode The AO bit (AUXR.0) in the AUXR register when set disables the ALE output. DPS BIT0 AUXR1 Reduced EMI Mode AUXR (8EH) 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 AO DPTR1 DPTR0 DPH (83H) DPL (82H) EXTERNAL DATA MEMORY AUXR.0 AO Turns off ALE output. Figure 13. SU00745A Dual DPTR The dual DPTR structure (see Figure 13) is a way by which the chip will specify the address of an external data memory location. There are two 16-bit DPTR registers that address the external memory, and a single bit called DPS = AUXR1/bit0 that allows the program code to switch between them. DPTR Instructions The instructions that refer to DPTR refer to the data pointer that is currently selected using the AUXR1/bit 0 register. The six instructions that use the DPTR are as follows: INC DPTR MOV DPTR, #data16 MOV A, @ A+DPTR MOVX A, @ DPTR Increments the data pointer by 1 Loads the DPTR with a 16-bit constant Move code byte relative to DPTR to ACC Move external RAM (16-bit address) to ACC Move ACC to external RAM (16-bit address) Jump indirect relative to DPTR • New Register Name: AUXR1# • SFR Address: A2H • Reset Value: xxxx00x0B AUXR1 (A2H) 7 – 6 – 5 – 4 – 3 GF2 2 0 1 – 0 DPS MOVX @ DPTR , A JMP @ A + DPTR Where: DPS = AUXR1/bit0 = Switches between DPTR0 and DPTR1. Select Reg DPTR0 DPTR1 DPS 0 1 The data pointer can be accessed on a byte-by-byte basis by specifying the low or high byte in an instruction which accesses the SFRs. See application note AN458 for more details. The DPS bit status should be saved by software when switching between DPTR0 and DPTR1. The GF0 bit is a general purpose user-defined flag. Note that bit 2 is not writable and is always read as a zero. This allows the DPS bit to be quickly toggled simply by executing an INC AUXR1 instruction without affecting the GF2 bit. 1999 Oct 27 19 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4K/8K/16K/32K Flash 89C51/89C52/89C54/89C58 ABSOLUTE MAXIMUM RATINGS1, 2, 3 PARAMETER Operating temperature under bias Storage temperature range Voltage on EA/VPP pin to VSS Voltage on any other pin to VSS Maximum IOL per I/O pin RATING 0 to +70 or –40 to +85 –65 to +150 0 to +13.0 –0.5 to +6.5 15 UNIT °C °C V V mA Power dissipation (based on package heat transfer limitations, not device power consumption) 1.5 W NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied. 2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. 3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. AC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C or –40°C to +85°C SYMBOL 1/tCLCL PARAMETER Oscillator frequency: U (33MHz) CLOCK FREQUENCY RANGE –f MIN 0 MAX 33 MHz UNIT 1999 Oct 27 20 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4K/8K/16K/32K Flash 89C51/89C52/89C54/89C58 DC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C or –40°C to +85°C; 5 V ±10%; VSS = 0 V SYMBOL VIL VIH VIH1 VOL VOL1 VOH VOH1 IIL ITL ILI ICC Input low voltage Input high voltage (ports 0, 1, 2, 3, EA) Input high voltage, XTAL1, RST Output low voltage, ports 1, 2, 3 8 Output low voltage, port 0, ALE, PSEN 7, 8 Output high voltage, ports 1, 2, 3 3 Output high voltage (port 0 in external bus mode), ALE9, PSEN3 Logical 0 input current, ports 1, 2, 3 Logical 1-to-0 transition current, ports 1, 2, 36 Input leakage current, port 0 Power supply current (see Figure 21): Active mode (see Note 5) Idle mode (see Note 5) Power-down mode or clock stopped (see Figure 25 for f conditions) diti ) Internal reset pull-down resistor Pin capacitance10 (except EA) VCC = 4.5 V IOL = 1.6 mA2 VCC = 4.5 V IOL = 3.2 mA2 VCC = 4.5 V IOH = –30 µA VCC = 4.5 V IOH = –3.2 mA VIN = 0.4 V VIN = 2.0 V See Note 4 0.45 < VIN < VCC – 0.3 See Note 5 VCC – 0.7 VCC – 0.7 –1 –75 –650 ±10 PARAMETER TEST CONDITIONS 4.5 V < VCC < 5.5 V LIMITS MIN –0.5 0.2 VCC+0.9 0.7 VCC TYP1 UNIT MAX 0.2 VCC–0.1 VCC+0.5 VCC+0.5 0.4 0.4 V V V V V V V µA µA µA Tamb = 0°C to 70°C Tamb = –40°C to +85°C 40 3 100 125 225 15 µA µA kΩ pF RRST CIO NOTES: 1. Typical ratings are not guaranteed. The values listed are at room temperature, 5 V. 2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOLs of ALE and ports 1 and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. IOL can exceed these conditions provided that no single output sinks more than 5 mA and no more than two outputs exceed the test conditions. 3. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the VCC–0.7 specification when the address bits are stabilizing. 4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 2 V. 5. See Figures 22 through 25 for ICC test conditions and Figure 21 for ICC vs Freq. Active mode: ICC(MAX) = (0.9 × FREQ. + 20)mA Idle mode: ICC(MAX) = (0.37 × FREQ. +1.0)mA 6. This value applies to Tamb = 0°C to +70°C. 7. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80 pF. 8. Under steady state (non-transient) conditions, IOL must be externally limited as follows: 15 mA (*NOTE: This is 85°C specification.) Maximum IOL per port pin: Maximum IOL per 8-bit port: 26 mA 71 mA Maximum total IOL for all outputs: If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 9. ALE is tested to VOH1, except when ALE is off then VOH is the voltage specification. 10. Pin capacitance is characterized but not tested. Pin capacitance is less than 25 pF. Pin capacitance of ceramic package is less than 15 pF (except EA is 25 pF). 1999 Oct 27 21 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4K/8K/16K/32K Flash 89C51/89C52/89C54/89C58 AC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C or –40°C to +85°C, VCC = 5 V ±10%, VSS = 0V1, 2, 3 VARIABLE CLOCK4 SYMBOL 1/tCLCL tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tPLAZ Data Memory tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tQVWX tWHQX tQVWH tRLAZ tWHLH tCHCX tCLCX tCLCH tCHCL Shift Register tXLXL tQVXH tXHQX tXHDX 17 17 17 17 Serial port clock cycle time Output data setup to clock rising edge Output data hold after clock rising edge Input data hold after clock rising edge 12tCLCL 10tCLCL–133 2tCLCL–80 0 360 167 50 0 ns ns ns ns 15, 16 15, 16 15, 16 15, 16 15, 16 15, 16 15, 16 15, 16 15, 16 15, 16 15, 16 16 15, 16 15, 16 18 18 18 18 RD pulse width WR pulse width RD low to valid data in Data hold after RD Data float after RD ALE low to valid data in Address to valid data in ALE low to RD or WR low Address valid to WR low or RD low Data valid to WR transition Data hold after WR Data valid to WR high RD low to address float RD or WR high to ALE high High time Low time Rise time Fall time tCLCL–25 17 17 3tCLCL–50 4tCLCL–75 tCLCL–30 tCLCL–25 7tCLCL–130 0 tCLCL+25 tCLCL–tCLCX tCLCL–tCHCX 5 5 5 0 2tCLCL–28 8tCLCL–150 9tCLCL–165 3tCLCL+50 40 45 0 5 80 0 55 6tCLCL–100 6tCLCL–100 5tCLCL–90 0 32 90 105 140 82 82 60 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns FIGURE 14 14 14 14 14 14 14 14 14 14 14 14 PARAMETER Oscillator frequency Speed versions: ALE pulse width Address valid to ALE low Address hold after ALE low ALE low to valid instruction in ALE low to PSEN low PSEN pulse width PSEN low to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address to valid instruction in PSEN low to address float 0 tCLCL–25 5tCLCL–80 10 tCLCL–25 3tCLCL–45 3tCLCL–60 0 5 70 10 I;J;U (33 MHz) 2tCLCL–40 tCLCL–25 tCLCL–25 4tCLCL–65 5 45 30 MIN 3.5 MAX 33 3.5 21 5 5 55 33 33MHz CLOCK MIN MAX UNIT MHz ns ns ns ns ns ns ns ns ns ns ns External Clock tXHDV 17 Clock rising edge to input data valid 10tCLCL–133 167 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF. 3. Interfacing the microcontroller to devices with float times up to 45 ns is permitted. This limited bus contention will not cause damage to Port 0 drivers. 4. Parts are guaranteed to operate down to 0 Hz. 1999 Oct 27 22 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4K/8K/16K/32K Flash 89C51/89C52/89C54/89C58 EXPLANATION OF THE AC SYMBOLS Each timing symbol has five characters. The first character is always ‘t’ (= time). The other characters, depending on their positions, indicate the name of a signal or the logical status of that signal. The designations are: A – Address C – Clock D – Input data H – Logic level high I – Instruction (program memory contents) L – Logic level low, or ALE P – PSEN Q – Output data R – RD signal t – Time V – Valid W – WR signal X – No longer a valid logic level Z – Float Examples: tAVLL = Time for address valid to ALE low. tLLPL =Time for ALE low to PSEN low. tLHLL ALE tAVLL tLLPL PSEN tPLPH tLLIV tPLIV tPLAZ tPXIX INSTR IN tLLAX tPXIZ PORT 0 A0–A7 A0–A7 tAVIV PORT 2 A0–A15 A8–A15 SU00006 Figure 14. External Program Memory Read Cycle ALE tWHLH PSEN tLLDV tLLWL RD tRLRH tAVLL PORT 0 tLLAX tRLAZ A0–A7 FROM RI OR DPL tRLDV tRHDX DATA IN tRHDZ A0–A7 FROM PCL INSTR IN tAVWL tAVDV PORT 2 P2.0–P2.7 OR A8–A15 FROM DPF A0–A15 FROM PCH SU00025 Figure 15. External Data Memory Read Cycle 1999 Oct 27 23 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4K/8K/16K/32K Flash 89C51/89C52/89C54/89C58 ALE tWHLH PSEN tLLWL WR tWLWH tAVLL PORT 0 tLLAX tQVWX tQVWH tWHQX A0–A7 FROM RI OR DPL DATA OUT A0–A7 FROM PCL INSTR IN tAVWL PORT 2 P2.0–P2.7 OR A8–A15 FROM DPF A0–A15 FROM PCH SU00026 Figure 16. External Data Memory Write Cycle INSTRUCTION ALE 0 1 2 3 4 5 6 7 8 tXLXL CLOCK tQVXH OUTPUT DATA 0 WRITE TO SBUF tXHQX 1 2 3 4 5 6 7 tXHDV INPUT DATA VALID CLEAR RI VALID tXHDX SET TI VALID VALID VALID VALID VALID VALID SET RI SU00027 Figure 17. Shift Register Mode Timing VCC–0.5 0.45V 0.7VCC 0.2VCC–0.1 tCHCL tCLCX tCLCL tCHCX tCLCH SU00009 Figure 18. External Clock Drive 1999 Oct 27 24 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4K/8K/16K/32K Flash 89C51/89C52/89C54/89C58 VCC–0.5 0.2VCC+0.9 VLOAD 0.2VCC–0.1 VLOAD+0.1V VLOAD–0.1V TIMING REFERENCE POINTS VOH–0.1V VOL+0.1V 0.45V NOTE: AC inputs during testing are driven at VCC –0.5 for a logic ‘1’ and 0.45V for a logic ‘0’. Timing measurements are made at VIH min for a logic ‘1’ and VIL max for a logic ‘0’. NOTE: For timing purposes, a port is no longer floating when a 100mV change from load voltage occurs, and begins to float when a 100mV change from the loaded VOH/VOL level occurs. IOH/IOL ≥ ±20mA. SU00717 SU00718 Figure 19. AC Testing Input/Output Figure 20. Float Waveform 60 50 40 Icc MAX. ACTIVE MODE ICC (mA) 30 Icc MAX ACTIVE MODE (TYP.) 20 Icc MAX. IDLE MODE 10 Icc IDLE MODE (TYP.) 4 8 12 16 20 24 28 32 36 Frequency at XTAL1 (MHz) SU01056 Figure 21. ICC vs. FREQ Valid only within frequency specifications of the device under test 1999 Oct 27 25 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4K/8K/16K/32K Flash 89C51/89C52/89C54/89C58 VCC ICC VCC VCC P0 EA (NC) CLOCK SIGNAL XTAL2 XTAL1 VSS (NC) CLOCK SIGNAL XTAL2 XTAL1 VSS VCC RST P0 EA VCC VCC ICC VCC RST SU00719 SU00720 Figure 22. ICC Test Condition, Active Mode All other pins are disconnected Figure 23. ICC Test Condition, Idle Mode All other pins are disconnected VCC–0.5 0.45V 0.7VCC 0.2VCC–0.1 tCHCL tCLCX tCLCL tCHCX tCLCH SU00009 Figure 24. Clock Signal Waveform for ICC Tests in Active and Idle Modes tCLCH = tCHCL = 5ns VCC ICC VCC RST P0 EA (NC) XTAL2 XTAL1 VSS VCC SU00016 Figure 25. ICC Test Condition, Power Down Mode All other pins are disconnected. VCC = 2V to 5.5V 1999 Oct 27 26 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4K/8K/16K/32K Flash 89C51/89C52/89C54/89C58 Security The security feature protects against software piracy and prevents the contents of the FLASH from being read. The Security Lock bits are located in FLASH. The 89C51/89C52/89C54/89C58 has 3 programmable security lock bits that will provide different levels of protection for the on-chip code and data (see Table 8). Unlike the ROM and OTP versions, the security lock bits are independent. LB3 includes the security protection of LB1. Table 8. SECURITY LOCK BITS1 Level LB1 LB2 LB3 PROTECTION DESCRIPTION DESCRIPTION MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory. Program verification is disabled External execution is disabled. NOTE: 1. The security lock bits are independent. 1999 Oct 27 27 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4K/8K/16K/32K Flash 89C51/89C52/89C54/89C58 PLCC44: plastic leaded chip carrier; 44 leads SOT187-2 1999 Oct 27 28 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4K/8K/16K/32K Flash 89C51/89C52/89C54/89C58 DIP40: plastic dual in-line package; 40 leads (600 mil) SOT129-1 1999 Oct 27 29 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4K/8K/16K/32K Flash 89C51/89C52/89C54/89C58 QFP44: plastic quad flat package; 44 leads 1999 Oct 27 30 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4K/8K/16K/32K Flash 89C51/89C52/89C54/89C58 NOTES 1999 Oct 27 31 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4K/8K/16K/32K Flash 89C51/89C52/89C54/89C58 Data sheet status Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Production [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 © Copyright Philips Electronics North America Corporation 1999 All rights reserved. Printed in U.S.A. Date of release: 10-99 Document order number: 9397–750–06613 Philips Semiconductors 1999 Oct 27 32 ...
View Full Document

This document was uploaded on 01/12/2011.

Ask a homework question - tutors are online