# Digital Design (4th Edition)

This preview shows pages 1–5. Sign up to view the full content.

1 Gate-Level Minimization Chapter 3 By Suleyman TOSUN Ankara University Outline s Intro to Gate-Level Minimization s The Map Method s 2-3-4-5 variable map methods s Product-of-Sums Method s Don’t care Conditions s NAND and NOR Implementations

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
2 Gate-Level Minimization s Finding an optimal gate-level implementation of Boolean functions. b Difficult to perform manually. b Can use computer-based logic synthesis tool s Exp: espresso logic minimization software b Karnough Map (K-map) can be used for manual design of digital circuits. The Map Method s The truth table representation of a function is unique. s But, not the algebraic expression b Several versions of an algebraic expression exist. b Difficult to minimize algebraic functions manually. s The map method is a simple proceure to minimize Boolean functions. b Pictorial form of a truth table. b Called Karnough Map or K-Map .
3 Two-Variable Map s Four Minterms s Two variables s Four squares for four minterms s Figure b shows the relationship between the squares and the variables x and y . Two-Variable Map (Cont.) s May only be useful to represent 16 Boolean functions. b Exp: If m1=m2=m3=1 then m1+m2+m3=x’y+xy’+xy=x+y (OR function)

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
4 Three-Variable Map s There are 8 minterms for 3 variables. s So, there are 8 squares. s Minterms are arranged not in a binary sequence, but in sequence similar to the Gray code. Three-Variable Map (Cont.)
This is the end of the preview. Sign up to access the rest of the document.

{[ snackBarMessage ]}

### Page1 / 23

chapter3 - Gate-Level Minimization Mano Ciletti Chapter 3...

This preview shows document pages 1 - 5. Sign up to view the full document.

View Full Document
Ask a homework question - tutors are online