Unformatted text preview: again, V 1 and V 2 represent the input to the gate. This time, however, the transistors are not connected in series. The source connects to each tran-sistor separately. If either transistor allows the source signal to be grounded, the output is 0. Therefore, the output is high (binary 1) only when both V 1 and V 2 are low (binary 0), which is what we want for a NOR gate. An AND gate, as we pointed out earlier in this chapter, produces output that is exactly opposite of the NAND gate. Therefore, to construct an AND gate we simply pass the output of a NAND gate through an inverter (or NOT gate). That’s why AND gates are more complicated to construct than NAND gates: They require three transistors, two for the NAND and...
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This note was uploaded on 01/13/2011 for the course CSE 1550 taught by Professor Marianakant during the Fall '10 term at York University.
- Fall '10