Dale - Computer Science Illuminated 132

Dale - Computer Science Illuminated 132 - output from the...

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4.4 Circuits 105 Figure 4. 11 A block diagram of a multi- plexer with three select control lines D0 S0 S1 F S2 D1 D2 D3 D4 D5 D6 D7 Let’s look at an example. A block diagram of a mux is shown in Figure 4.11. The control lines S0, S1, and S2 determine which of eight other input lines (D0 through D7) are routed to the output (F). The values of the three control lines, taken together, are interpreted as a binary number, which determines which input line to route to the output. Recall from Chapter 2 that three binary digits can represent eight different values: 000, 001, 010, 011, 100, 101, 110, and 111. Note that these values simply count in binary from 0 to 7, which correspond to our output values D0 through D7. So if S0, S1, and S2 are all 0, the input line D0 would be the output from the mux. If S0 is 1, S1 is 0, and S2 is 1, then D5 would be
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Unformatted text preview: output from the mux. The following truth table shows how the input control lines determine the output for this multiplexer: The block diagram in Figure 4.11 hides a fairly complicated circuit to carry out the logic of a multiplexer. Such a circuit could be shown using eight three-input AND gates and one eight-input OR gate. We wont get into the details of the circuit in this book. A multiplexer can be designed with various numbers of input lines and corresponding control lines. In general, the binary values on n input control lines are used to determine which of 2 n other data lines are selected for output. S0 1 1 1 1 S1 1 1 1 1 S2 1 1 1 1 F D0 D1 D2 D3 D4 D5 D6 D7...
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This note was uploaded on 01/13/2011 for the course CSE 1550 taught by Professor Marianakant during the Fall '10 term at York University.

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