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Unformatted text preview: How to add a VHDL module to your design? For now, assume that you want to add the memory module (available on courseweb) to your design. The name of the module is my_memory. Simply follow these steps: 1‐ Copy the VHDL source file (my_memory.vhdl) to [your_project_folder]\pcores\video_capture\hdl\vhdl\ 2‐ Open [your_project_folder]\pcores\video_capture\data\video_capture.pao with a text editing program (Notepad) and add the following line to it: lib video_capture_v1_01_b my_memory 3‐ Save the project and restart EDK. ...
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This note was uploaded on 01/14/2011 for the course CS 152 taught by Professor Staff during the Fall '98 term at UCLA.
- Fall '98