lab3 - CS M152B - Lab 3 Part I: De-Interlacing Introduction...

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CS M152B - Lab 3 Part I: De-Interlacing Introduction In this lab, you will implement a module that performs de-interlacing as shown in the following figure. The NTSC video signal encodes each “frame” or picture of video on a horizontal line-by- line basis, and each scan line is a composite signal of brightness and color information. Digitally, a scan line is given as a set of picture elements (pixels). The NTSC video signal is “interlaced,” meaning that first all of the odd-numbered lines of the frame are given from top to bottom, and then the even-numbered lines. This design reduces “flicker.” “Progressive” video signal encodes the lines in order, but must run at a higher frame rate to reduce flicker. In this lab you will design a module that helps convert an interlaced digital video signal to a progressive video signal running at twice the frame rate of the original. De- interlacing For this laboratory assignment, you will use Xilinx ISE Foundation software to design and test the “de-interlace by line doubling” block.
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Implementation You are required to write a module called “deinterlace.vhd” that employs two “line_buffer.vhd” memory modules and performs de-interlacing by line doubling. The VHDL description of the “line_buffer.vhd” module is given in appendix A. You may need to modify this module slightly to simulate under ModelSim. The user of your module will write a sequence of pixels at 13.5 MHz and will simultaneously read a sequence of pixels at 27 MHz. Inside your de-interlacer a sequence of pixels will be written into one line buffer at 13.5 MHz and it will simultaneously read from the other line buffer at 27 MHz. When a line is completely written, it will switch buffers and read from the buffer that it was writing to previously, and vice versa. Because the read is happening at twice the rate of the write, the user will read the same line twice. “Line_buffer.vhd” uses BRAM primitives (RAMB16_S9_S9) for red, blue and green pixel data. Please see the libraries guide for more information about the BRAM primitives. You will need to instantiate two line buffers and use a double-buffering scheme. For your implementation assume that each line of video is 8 pixels. Specifications: The entity for “deinterlace” module is described below: ENTITY deinterlace IS PORT ( rst : IN std_logic; clk_13: IN std_logic; Ri : IN std_logic_vector (7 DOWNTO 0); Gi : IN std_logic_vector (7 DOWNTO 0); Bi : IN std_logic_vector (7 DOWNTO 0); clk_27: IN std_logic; Ro : OUT std_logic_vector (7 DOWNTO 0); Go : OUT std_logic_vector (7 DOWNTO 0);
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Bo : OUT std_logic_vector (7 DOWNTO 0); } Clk_13 and clk_27 are the clock signals for input and output streams respectively. Assume that these two clocks are in sync with one twice the frequency of the other. Rst resets the buffer switching logic. Throughout simulation with ModelSim, make sure that the clock periods match
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lab3 - CS M152B - Lab 3 Part I: De-Interlacing Introduction...

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