vhdl_F10 - VHDL Quick Start UCLA CS 152B Fall 2010 Modeling...

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VHDL Quick Start UCLA, CS 152B Fall 2010
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VHDL Quick Start 2 Modeling Digital Systems VHDL is for Hardware Description Language used for: Documentation Specification Simulation Computer Aided Design (Design Automation) Synthesis Formal Verification Placement & Routing Test Generation Other automatic algorithms
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VHDL Quick Start 3 VHDL Modeling Modeling Entity Name, Interfaces Architecture Concurrent Statements Architecture Entity Ports Ports Some VHDL structures are not Synthesizable Time high level structures used for testbench generation or just modeling (file, pointers, function, ..)
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VHDL Quick Start 4 Modeling Interfaces Entity declaration Port Generic entity entity_name is generic (parameter: type := exp); port (port_names: port_mode type; .. ); end entity_name; entity counter is generic (size : integer := 4); port (clock : in bit; q : out bit_vector(size-1 downto 0)); end counter;
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VHDL Quick Start 5 Types Frequently used types bit, bit_vector: 2-value logic system std_logic, std_logic_vector: 9-value logic system Integer, natural, time, .. You can also define a type yourself! Vector Ranges (0 to 3) (7 downto 2) For std_logic type: library ieee; use ieee.std_logic_1164.all;
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VHDL Quick Start 6 Port Mode IN OUT INOUT BUFFER
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VHDL Quick Start 7 Hardware Description Architecture body describes functionality of the entity may be several per entity (for synthesis just select one!) Behavioral architecture Contains Concurrent Statements Concurrent Signal Assignment Process Statement Component Instantiation Note1: Concurrent statements cannot be inside each other! Note2: Concurrent statements work when observe an event on at least one of the elements on their sensitivity list
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VHDL Quick Start 8 Concurrent Signal Assignment target <= waveform;
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