my_memory -...

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Unformatted text preview: ----------------------------------------------------------------------------------------------Design name : my_memory ----------------------------------------------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; u use IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY MY_MEMORY IS PORT ( clk read_address write_address read_data write_enable write_data E END MY_MEMORY; : IN std_logic; : IN std_logic_vector(12 DOWNTO 0); : IN std_logic_vector(12 DOWNTO 0); : OUT std_logic_vector(7 DOWNTO 0); : IN std_logic; : IN std_logic_vector(7 DOWNTO 0)); ARCHITECTURE behavioral OF MY_MEMORY IS type ram_type is array (8191 DOWNTO 0) of std_logic_vector (7 downto 0); signal RAM : ram_type; signal read_a : std_logic_vector(12 downto 0); signal read_dpra : std_logic_vector(12 downto 0); begin process (clk) begin if (clk'event and clk = '1') then if (write_enable = '1') then RAM(conv_integer(write_address)) <= write_data; end if; read_a <= read_address; end if; end process; read_data <= RAM(conv_integer(read_a)); END behavioral; ...
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This note was uploaded on 01/14/2011 for the course CS 152 taught by Professor Staff during the Fall '98 term at UCLA.

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