UC Berkeley, EECS Department
B. E. Boser
EECS 40
HW11: Digital Circuits
UID:
1. Convert the binary number 10110110 to decimal.
1 pt.
0
2. Convert the decimal number
to binary.
1 pt.
1
3. Evaluate the boolean expression
Y
=
A
+
B
C
for
A
=
0,
B
=
1, and
C
=
0.
1 pt.
2
4. Calculate the propagation delay
t
d
for a minimum size inverter driving another minimum size inverter, both
with
R
on
=
k
Ω
and
C
g
=
fF (use the same numbers for transistors with true and inverted control).
The propagation delay from
v
in
to
v
out
is the time required for the output to reach 50 % of its final output
level when the input changes, as illustrated in the figure below.
To simplify the analysis, assume that the transistors switch abruptly between the on and off states when the
voltage at the gate reaches 50 % of
V
dd
. Although this is only an approximation, the results are still very
useful for proper transistor sizing.
In practice one would use SPICE to verify the exact timing, possibly
making small adjustments based on the numerical result.
t
d
=
1 pt.
3
5. Design a transistor level circuit for a CMOS NOR gate. This gate is used in the ALU (arithmetic and logic
unit) of a microprocessor. Its output is capacitively loaded with
C
1
=
fF as shown in the diagram below.
The capacitance comes from the input of other gates connected to the output of the NOR gate and from
wiring parasitics. The propagation delay of the gate is defined as the worst case delay incurred when any of
the two inputs
A
or
B
changes (logic 0
→
1 or 1
→
0) for the output
Y
of the gate to reach 50 % of its final
value. Model the transistors in the gate with
k
Ω
resistors in the onstate, and open circuits in the offstate.
Calculate the worstcase propagation delay
t
d
of the gate for low to high and high to low transitions of the
input.
The delay of the gate depends on input transitions. For example, input A changing from 0 to 1 with B=0
results in a particular delay
t
d
1
. The delay with A changing from 0 to 1 with B=1 results in delay
t
d
1
, A
changing from 1 to 0 with B=0 and 1 respectively in delays
t
d
3
and
t
d
4
. For more situations are possible with
B transitioning and A being either 0 and 1. For many gates these delays (such as the NOR gate we designed),
these delays differ. The “worstcase delay” is defined as the maximum value
t
d
of all possible delays
t
di
.
This preview has intentionally blurred sections. Sign up to view the full version.
View Full Document
This is the end of the preview.
Sign up
to
access the rest of the document.
 Fall '07
 ChangHasnain
 Integrated Circuit, Transistor, Clock signal, Logic gate

Click to edit the document details