CMOS - C:\Users\Bernhard Boser\Documents...

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C:\Users\Bernhard Boser\Documents \Files\Class\40\lecture\notes 4/10/2008 Page 1 of 6 Reference:W:\Lib\MathCAD\Default\defaults.mcd Transistors, CMOS, Moore's Law 1) Logic gates (circuit) realization of boolean functions logic signal levels signal restoration cascading logic gates 2) Transistors MOSFETs Operation Operation as switch Fabrication 3) Moore's Law Transistors per chip Transistor size Circuit speed Cost V DD V SS Logic “1” Logic “0” ? 1) CMOS Logic Gates Signal levels: - VDD/VSS for 1 and 0 - "safety zone" inbetween - noise, signal restoration - cascadability Gates: - output connected to either 0 or 1 for any combination of inputs - output never connected to both 0 and 1 Examples: inverter, NOR, 3-input NAND NOR ABO R N O R 000 1 011 0 101 0 111 0
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C:\Users\Bernhard Boser\Documents \Files\Class\40\lecture\notes 4/10/2008 Page 2 of 6 2) MOS Transistor MOSFET - nmos example - "basic" physics: carrier density modulation with capacitively coupled gate) - symbols - nmos, pmos - operation as switch
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This note was uploaded on 01/15/2011 for the course EE 40 taught by Professor Chang-hasnain during the Spring '07 term at University of California, Berkeley.

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CMOS - C:\Users\Bernhard Boser\Documents...

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