Lecture05 - The Design-Oriented Approach to Electronic...

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Unformatted text preview: The Design-Oriented Approach to Electronic Circuits Camenzind: Designing Analog Chips Lecture 5 Chapter 1: Devices Parasitic Elements in BJTs In an integrated circuit, devices are isolated from each other either by insulators such as silicon dioxide, or by reverse-biased PN junctions. The isolation structures inevitably create some parasitic elements: devices that are ontacts on nintentionally inemitter and lengthen the emitter. place base c formed u both sides of the the design of the desired structure. For example, oxide-isolated layers arethe left is the top view of a minimum-geometry transistor Shown here on inevitably connected through some capacitance to adjacent layers. If the oxide on thick enough, these capacitances may be small enough to neglect. and is the right a version for higher current. T make the life of a and surprising parasitic elements. We've Junction isolation, however, canoproduce complex designer easier, the isolation pattern is usually djunctionacapacitance, and how it can be reduced the mask, i.e. the rawn as rectangle and then inverted when making by using light doping already talked about PN isolation diffusion is actually between devices, not in the device area. on the less-heavily doped side of the junction. Reverse-biased PN junctions also have leakage Many processes require that all contacts be the same size, in which currents. Junction leakage currents are usually quite small, often p into small,amp range or lower. case the contact rectangles must be broken u in the pico- identical (and However, they increase papidly as temperature increases (typically doubling for each 10 °C rise r roperly spaced) squares. in temperature). Be aware, that transistors of different sizes (as drawn here) do not match well. normally reverse-biased junctions become forward-biased. Things can get more complicated if At low current a large emitter area produces a higher gain than a small one, because the minority carriers have a higher chance to be Usually circuits are designed so that such junctions don't become forward-biased in normal captured by the collector. If you want to produce a precise ratio, use only operation. However, theocircuit designer must prepare for unusualThe emitterssuchbe in a the situations can as when ne emitter size and identical base contacts. power supplies and inputommon base applied in certain orders is of no consequence except for c signals are area and the collector size or during peak signal excursions. If an isolating junction getsollector resistance enough current could flow to burn out the device. It's c forward-biased, (or saturation voltage). important to think about the paths (possibly two-.oThere isdimensional)current across the take as Substrate Current r three- only leakage such currents will they flow through the well or substrate to junction,contacts. Ittransistor saturates. collector-substrate nearby unless the is possible that such currents can change the operating points of Assume devices, whichconnected through a resistor toway positive nearby the collector is can cause problems a long the from the supply voltage and the base is driven so hard that the collector voltage drops original junction. Even more complex parasitic behavior can occur when parasitic BJTs saturation). are formed from adjacent PNP There arelnow two diodes in parallel and or NPN ayers. If a junction of one of these BJTs becomes forward-biased, amplification can occurone forms a the base current has two paths; the new with unintended consequences. For example, the standard vertical NPN PNP transistor with the NPN base becoming the emitter, the NPN collector structure contains a parasitic vertical PNP using the base and the NPN's base, substrate the collector. Since the NPN collector is collector and the substrate as the PNP's emitter, base and collector, much larger than when the NPN saturates, respectively. The parasitic PNP turns onits emitter, some (or all) of the base current flows to the substrate. sending current that would have flowed in the NPN's emitter into the There is little danger in this, except when substrate. Any time current flows in the substrate, you should be you drive the base very hard, trying to get the wary: if the resistivity of the substrate is high enough, the local lowest possible collector voltage, or if you have voltage in the substrate can be significantly higher than The path in the many saturating NPN transistors. expected, changing the operating point of nearby transistor to the -V connection has substrate from a devices. to near the potential of the emitter (termed Collector Base NPN PNP Emitter Substrate Fig. 1-14: When an NPN transistor saturates a stray PNP device leaks current to the substrate. Similarly, lateral PNP's somestandard process include vertical is so large can lower the effective in a resistance. If the substrate current PNPs that that the voltage cause substrate current can with hard-to-predict results. beta of the lateral PNP and once again drop across this resistanceflow forward-bias some substratecollector junction on the way, you may get some really bad effects, One of the most serious iproblemslatch-up. can happen if a four-layer stack of PNPN layers exists. ncluding is what Maximum Voltage postitive feedback loop that requires high Under some conditions, such structures can form .a To get a high operating voltagecan force the resistivityupow doping concentration. But there is a price to be paid: the transistors into a so-called latch- - l state, in which large and possibly destructive currents flow. depletion regions become wide. Even if latch-up is not destructive, the device may not work properly until the latch-up condition is removed, typically by turning off the power supplies. Obviously this is not good, and you as the circuit designer don’t want to get blamed for it, so be on the lookout for this possibility! Edition February 2005 1-20 All rights reserved ...
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This note was uploaded on 01/17/2011 for the course EEE 5320 taught by Professor Dr.robertfox during the Fall '10 term at University of Florida.

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