EEL6323-S10-HLec05-LogicalEffort-4spp - Lecture 5: Logical...

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1 Lecture 5: Logical Effort Logical Effort (g, h, p) Examples Reading: Ch. 4 Introduction Chip designers face a bewildering array of choices – What is the best circuit topology for a function? – How many stages of logic give least delay? – How wide should the transistors be? Logical effort is a method to make these decisions – Uses a simple model of delay – Allows back-of-the-envelope calculations – Helps make rapid comparisons between alternatives – Emphasizes remarkable symmetries ? ? ? Conceptual Model of a CMOS Logic gate Model of a logic gate Cin=input terminal capacitance Ruo=pull-up resistance of pull-up network Rdo=pull-down resistance Cpo=parasitic output capacitance Cout=load capacitance presented by the input capacitance of logic gates it drives k g s d k g s d Template Gate Assume every logic gate is a scaled version of template gate Assume a template gate with k g s d k g s d s d C in C out C po s R uO R dO t in C k C k R R R R t do uo o pt po C k C in out Wn/Ln Wp/Lp Template Gate P P N N t L W k L W k C 1 1 P P P N N N t L W k L W k R 2 2 1
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This note was uploaded on 01/17/2011 for the course EEL 6323 taught by Professor Bashirullah during the Spring '08 term at University of Florida.

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EEL6323-S10-HLec05-LogicalEffort-4spp - Lecture 5: Logical...

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