EEL6323-S10-HLec06-MultiStageLE-P1-4spp

# EEL6323-S10-HLec06-MultiStageLE-P1-4spp - Lecture 6:...

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1 Lecture 6: Multistage Logic Networks Multistage Logic Networks Reading: Ch. 4 Multistage Logic Networks Path Logical Effort 10 x y z 20 g 1 = h 1 = g 2 = h 2 = g 3 = h 3 = g 4 = h 4 = Multistage Logic Networks Path Electrical Effort 10 x y z 20 g 1 = 1 h 1 = g 2 = 5/3 h 2 = g 3 = 4/3 h 3 = g 4 = 1 h 4 = Multistage Logic Networks Logical effort generalizes to multistage networks 10 x y z 20 g 1 = 1 h 1 = x/10 g 2 = 5/3 h 2 = y/x g 3 = 4/3 h 3 = z/y g 4 h 4 = 20/z

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2 Paths that Branch Consider paths that branch: G = H = GH = h 1 = h 2 = F = 5 15 15 90 90 Branching Effort Introduce branching effort The branching effort is: Paths that Branch Consider paths that branch: G = H = B = GBH = h 1 = h 2 = F = 5 15 15 90 90 Path Effort Path Logical Effort Path Electrical Effort Branching Effort Path Effort Note:
3 Multistage Delays Path Effort Delay Path Parasitic Delay Path Delay Designing Fast Circuits Delay is smallest when each stage bears same effort Thus minimum delay of N stage path is This is a key result of logical effort iF Dd D P  Example: 3-stage path

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## This note was uploaded on 01/17/2011 for the course EEL 6323 taught by Professor Bashirullah during the Spring '08 term at University of Florida.

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EEL6323-S10-HLec06-MultiStageLE-P1-4spp - Lecture 6:...

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