EEL6323-S10-HLec07-MultiStageLE-P2-4spp

# EEL6323-S10-HLec07-MultiStageLE-P2-4spp - Lecture 7:...

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1 Lecture 7: Multistage Logic Networks Multistage Logic Networks (cont. from Lec 06) Examples Reading: Ch. 4 Example: 3-stage path Logical Effort G = (4/3)*(5/3)*(5/3) = 100/27 Electrical Effort H = 45/8 Branching Effort B = 3 * 2 = 6 Path Effort F = GBH = 125 Best Stage Effort Parasitic Delay P = 2 + 3 + 2 = 7 Delay D = 3*5 + 7 = 22 = 4.4 FO4 8 x x x y y 45 A B 3 ˆ 5 fF Select gate sizes x and y for least delay from A to B Example: 3-stage path Work backward for sizes y = 45 * (5/3) / 5 = 15 x = (15*2) * (5/3) / 5 = 10 P: 4 N: 4 45 45 A B P: 4 N: 6 P: 12 N: 3 Best Number of Stages How many stages should a path use? – Minimizing number of stages is not always fastest Example: drive 64-bit datapath with unit inverter D = NF 1/N + P = N(64) 1/N + N 1111 84 16 8 2.8 23 64 Initial Driver Datapath Load N: f: D: 1 65 2 8 18 3 4 15 4 2.8 15.3 Fastest F=GBH B=1 H=64 G=1

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2 Best Stage Effort Derivation Consider adding inverters to end of path – How many give least delay? Define best stage effort Neglecting parasitics (p inv = 0), we find = 2.718 (e) For p inv = 1, solve numerically for = 3.59 N - n 1 Ex tr a Inverters Logic Block: n 1 Stages Path Ef f or t F  1 1 1 1 N n ii n v i DN F p Nnp  111 ln 0 NNN inv D FFFp N  1l n 0 inv p  1 N F No closed-form solution Sensitivity Analysis How sensitive is delay to using exactly the best number of stages? 2.4 < < 6 gives delay within 15% of optimal – We can be sloppy!
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## This note was uploaded on 01/17/2011 for the course EEL 6323 taught by Professor Bashirullah during the Spring '08 term at University of Florida.

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EEL6323-S10-HLec07-MultiStageLE-P2-4spp - Lecture 7:...

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