EEL6323-S10-HLec08-DigitalFLow-I-4spp

EEL6323-S10-HLec08-DigitalFLow-I-4spp - Hierarchy of design...

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1 Overview of Digital IC Design Flow By Chung-Ching Peng Hierarchy of design abstractions Specification Behavior (Algorithm) Register-Transfer (Arch.) Logic (Gate) Circuit (Transistor) Layout Front-end design Back-end design (Physical design) VHDL/Verilog VHDL/Verilog/EDIF SPICE GDSII C,C++/VHDL/Verilog Matlab/SystemC System design State Charts/UML/ SystemC/SystemVerilog Technology Dependent Top-Down Design Methodology Description of Design Abstract
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2 Description of Design Abstract (cont’d) Description of Design Abstract (cont’d) SOC Design Flow EDA Market From EDN.com 12/2007 Overall EDA market grows very slowly. • The only two growth areas in the EDA market: (1) Design for Manufacturability / Yield (DFM / DFY) (2) Pre-synthesis part of the flow that includes System-Level design, Hardware-Software Codesign, and Prototyping.
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3 EDA Tools Grouped by Functions Synopsys Formality Formal Verification Cadence, Magma, Synopsys Celtic, Blast Noise, PrimeTime Signal Integrity Analysis Cadence, Synopsys, Magma Encounter, Astro, Blast Fusion IC Auto Place/Route Mentor, Cadence, Synopsys Calibre, Diva, Star-RCXT RC Extraction Mentor, Cadence, Synopsys Calibre, Diva/Assura, Hercules IC Layout Verification Cadence, Agilent Virtuoso, ADS IC Layout Synopsys, Mentor Nanosim, Mach TA Dynamic Timing Analysis Synopsys, Cadence PrimeTime, Encounter Timing Static Timing Analysis Mentor, Mentor, Synopsys Fastscan, Flextest, Tetramax DFT and ATPG Tools Synopsys, Cadence, Magma PrimePower, VoltageStorm, Blast Rail Power Analysis Synopsys, Cadence, Synplicity Design Compiler, Encounter RTL Compiler, Synplify Logic Synthesis Mentor, Cadence Modelsim, NC-VHDL VHDL Simulation Mentor, Cadence, Synopsys Modelsim, Verilog XL/NC- Verilog, VCS Verilog Simulation Vendors Tools Functions UMC-Cadence Digital Reference Flow 1. Standard Cell Library •A standard cell library
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This note was uploaded on 01/17/2011 for the course EEL 6323 taught by Professor Bashirullah during the Spring '08 term at University of Florida.

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EEL6323-S10-HLec08-DigitalFLow-I-4spp - Hierarchy of design...

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