EEL6323-S10-HLec09-DigitalFLow-II-4spp

EEL6323-S10-HLec09-DigitalFLow-II-4spp - 3. Logic Synthesis...

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1 3. Logic Synthesis • Use a HDL (VHDL or Verilog) and a synthesis tool to produce a gate-level netlist – a description of the logic cells and their connections. Synthesis is Constraint-Driven Technology Independent Logic Synthesis Overview
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2 Logic Synthesis Input/Output Design Compiler How to run it ? 1. dc_shell (recommended): The command-line interfaces for synthesis and timing analysis. A set of command can be put together into a file called “script”. Don’t need to re-type the commands again and again when using dc_shell. 2. Graphic user interface (GUI). • What is Design Compiler? The Role of Design Compiler Synthesize the design Carry out a preliminary, or default, synthesis 3.1 Design Environment Why describes the Real World Environment?
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3 Describing Design Environment Operating Condition 3.2 Design Constraints 3.3 Gate-Level Optimization
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4 • Formal verification is the use of mathematical techniques to ensure that a design conforms to some precisely expressed notion of functional correctness. • A particular formal verification problem of great interest in EDA is equivalence checking. • Why “Formal Verification”
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This note was uploaded on 01/17/2011 for the course EEL 6323 taught by Professor Bashirullah during the Spring '08 term at University of Florida.

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EEL6323-S10-HLec09-DigitalFLow-II-4spp - 3. Logic Synthesis...

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