EEL6323-S10-HLec010-DigitalFLow-III-4spp

EEL6323-S10-HLec010-DigitalFLow-III-4spp - Todays Lecture...

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1 Today’s Lecture Part I: Digital IC Design Tools Tutorials (1) RTL Simulation Cadence NCSim (2) Logic Synthesis Synopsys Design Compiler (3) Physical Implementation Cadence SOC Encounter Part II: Synthesizable RTL Coding NCLaunch Tutorial (1/12) Log in to your ECEL account. Create a design folder, we use /VLSI_SP09/RTL in the following example. Upload your VHDL/Verilog codes into your design folder. In the command window, type the following > source /cds/settings ius810 > cd VLSI_SP09/RTL NCLaunch Tutorial (2/12) NCLaunch Tutorial (3/12) File > Set Design Directory. Invoke the following 3 windows in sequence. 1 2 3
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2 NCLaunch Tutorial (4/12) Click to compile your VHDL /Verilog codes (including the testbench) NCLaunch Tutorial (5/12) Check to see your design and testbench are properly compiled. If there is any syntax error, it looks like this, Fix all the errors before you proceed. NCLaunch Tutorial (6/12) Click to elaborate your highest level entity, in this case it’s in testbench. The ncelab program constructs a design hierarchy NCLaunch Tutorial (7/12) Click to launch SimVision
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3 NCLaunch Tutorial (8/12) Check Waveform Check Schematic NCLaunch Tutorial (9/12) NCLaunch Tutorial (10/12) NCLaunch Tutorial (11/12)
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4 NCLaunch Tutorial (12/12) Design Compiler Tutorial (1/5) define_design_lib WORK -path /home/users/0/wuq/VLSI_SP09/SYN/WORK analyze -f VHDL /home/users/0/wuq/VLSI_SP09/SYN/FSM.vhd elaborate FSM current_design FSM link uniquify current_design FSM create_clock -period 10 Clock set_input_delay -clock Clock 1 SlowRAM set_output_delay -clock Clock 1 {Read Write} compile_dc Design Compiler Tutorial (2/5) compile verilogout_no_tri = true set_fix_multiple_port_nets -all -buffer_constants check_design report_constraint -all_violators write -f verilog -output FSM.v write_sdc FSM.sdc write_sdf -version 2.1 FSM.sdf write -hier -output FSM.db report_timing > timing.rep report_cell > cell.rep report_power > power.rep quit Design Compiler Tutorial (3/5) Log in to your ECEL account. Create a design folder, we use /VLSI_SP09/SYN in the following example. Upload your VHDL/Verilog codes, the script (compile_dc) and the .synopsys_dc.setup file into your design folder. In the command window, type the following > mkdir WORK > source /syn/settings synthesis > dc_shell –f compile_dc
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5 Design Compiler Tutorial (4/5) Design Compiler Tutorial (5/5) Check your .v netlist file. Below is the netlist synthesized from the FSM example. Encounter Tutorial (1/3) # Specify the name of your top level module set my_toplevel FSM encounter.conf # Create Initial Floorplan floorplan -r 1.0 0.6 40 40 40 40 encounter.tcl Encounter Tutorial (2/3) Create a design folder, we use /VLSI_SP09/PAR in the example. Upload the following files to your PAR folder
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This note was uploaded on 01/17/2011 for the course EEL 6323 taught by Professor Bashirullah during the Spring '08 term at University of Florida.

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EEL6323-S10-HLec010-DigitalFLow-III-4spp - Todays Lecture...

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