EEL6323-S10-HLec012-Power-dissipation-4spp

EEL6323-S10-HLec012-Power-dissipation-4spp - Lecture 12:...

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1 Lecture 12: Power Dissipation Power and Energy Dynamic Power Static Power Leakage Reading: Ch. 4 Power and Energy Power is drawn from a voltage source attached to the V DD pin(s) of a chip. Instantaneous Power: Energy: Average Power: () D DD D Pt i tV 00 TT DD DD E Ptd t i tV d t   avg 0 1 T DD DD E P it Vd t Dynamic Power One half of the power from the supply is consumed in the pull-up network and one half is stored on CL Charge from CL is dumped during the 1 0 transition 2 0 0 0 ) ( DD L VDD out DD L out L DD DD VDD VDD V C dv V C dt dt dv C V dt V t i E 2 ) ( 2 0 0 0 DD L VDD out out L out out L DD out VDD C V C dv v C dt v dt dv C V dt v t i E Dynamic Power Consumption Power = Energy/transition x transition rate = C L V DD 2 f 0 1 = C L V DD 2 f α 0 1 = C EFF V DD 2 f α 0 1 = switching activity rate – Switched capacitance – C EFF = C L x α 0 1 – Power dissipation is data dependent (switching probability) Activity over N cycles
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2 Examples of transition probabilities: NOR vs XOR Assume Signal Probabilities p A=1 = ½ p B=1 = ½ Transition Probability p 0 1 = p out=0 x p out=1 =±¾x±¼=±3/16 C EFF =3/16 x C L Static 2-input NOR gate Static 2-input XOR gate Assume Signal Probabilities p A=1 = ½ p B=1 = ½ Transition Probability p 0 1 = p out=0 x p out=1 = 1/2 x 1/2 = 1/4 C EFF =1/4 x C L Dynamic Example 200 Mtransistor chip – 20M logic transistors: Average width: 12 – 180M memory transistors: Average width: 4 – 1.2 V 100 nm process, C g = 2 fF/ m – Static CMOS logic gates: activity factor = 0.1 – Memory arrays: activity factor = 0.05 (many banks!)
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This note was uploaded on 01/17/2011 for the course EEL 6323 taught by Professor Bashirullah during the Spring '08 term at University of Florida.

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EEL6323-S10-HLec012-Power-dissipation-4spp - Lecture 12:...

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