EEL6323-S10-HLec014-Power-dissipation-4spp

EEL6323-S10-HLec014-Power-dissipation-4spp - 1 Lecture 14:...

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Unformatted text preview: 1 Lecture 14: Power Dissipation Low Power Design Throughput oriented design Clock gating Leakage reduction techniques Multi-processing trends Types of Processing Fixed-rate Processing (i.e. Signal processing for multimedia or communications) Stream based computation No advantage in obtaining throughput in excess of the real-time constraint Variable-rate or burst-mode computation (i.e. general purpose computation) Mostly idle (or low load) with bursts of computation Faster is better Common Design Approach: Fixed VDD Compute intensive:-video decompression-speech processing-matlab Low speed/long latency-text entry-playing music-address browsing Idle Dynamic Voltage Scaling (DVS) Reduce VDD Decrease frequency 2 Dynamic Power Reduction Through Software Hardware Cooperation Processor: Converter Loop sets V DD , f clk f 1MHz <<f clk accumulator Ring oscillator matched to critical path of processor System Performance and Energy Clock Distribution In P, roughly 40% of total power dissipated in clock distribution Processors have variable throughput Many blocks are idle Pentium 4 Clocking Scheme 3 Clock Gating Requires careful skew control Working with leakage Impact of Process Variations Significant variation in performance and leakage The most critical paths may be different from chip to chip Frequency binning Leakage reduction Stack Effect Sleep transistors (MTCMOS)...
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This note was uploaded on 01/17/2011 for the course EEL 6323 taught by Professor Bashirullah during the Spring '08 term at University of Florida.

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EEL6323-S10-HLec014-Power-dissipation-4spp - 1 Lecture 14:...

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