EEL6323-S10-HLec015-Circuit-Families-4spp - Lecture 15:...

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1 Lecture 15: Circuit Families Static CMOS and Compound Gates Asymmetric Gates Pseudo-nMOS Logic CVSL, PTL, LEAP, CPL Bubble Pushing Start with network of AND / OR gates Convert to NAND / NOR + inverters Push bubbles around to simplify logic – Remember DeMorgan’s Law Y Y Y D Y (a) (b) (c) (d) A B = A + B A + B = A B Compound Gates Example Calculate the min. delay to compute F=AB+CD using NAND and Compound gate designs. The multiplexer has a maximum input capacitance of 16 units on each input. It must drive a load of 160 units. Y D0 S D1 S H = 160 / 16 = 10 B = 1 N = 2 2x 2x 2x 2x 4x 4x Y 2x 1x 4x 4x p=2 g=4/3 p=2 g=4/3 p=12/3=4 g=6/3=2 p=1 g=1
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2 NAND Solution Compound Solution 224 (4/3) (4/3) 16/9 160 / 9 ˆ 4.2 ˆ 12.4 N P G FG B H fF DN fP    ± 415 (6/3) (1) 2 20 ˆ 4.5 ˆ 14 N P G B H   ± Y Y Asymmetric Gates Asymmetric gates favor one input over another Ex: suppose input A of a NAND gate is most critical – Downsize noncritical transistor on unimportant input – Reduces parasitic delay for critical input – Boost size of noncritical input (same R) Maintain equivalent pulldown resistance – Rd=R/4 + (¾)R=R –g A = 10/9, g B = 5/3 Asymmetric gate approaches g = 1 on critical input (but total logical effort goes up) A reset Y 4 4/3 2 1 reset A Y Symmetric Gates Data arrival time affects delay Outer input is closest to rail (B) Inner input is closest to output (A) If input arrival time is known – Connect latest input to inner terminal Inputs can be made perfectly symmetric 2 2 2 2 B A Y A B Y 2 1 1 2 1 1 HI- and LO-Skew Skewed gates favor one edge over another – HI-skew gates favor rising output (small nMOS) – LO-skew gates favor falling output (small pMOS) Logical effort is smaller for favored direction, but larger for the other direction
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This note was uploaded on 01/17/2011 for the course EEL 6323 taught by Professor Bashirullah during the Spring '08 term at University of Florida.

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EEL6323-S10-HLec015-Circuit-Families-4spp - Lecture 15:...

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