EEL6323-S10-HLec016-Circuit-Families-4spp

EEL6323-S10-HLec016-Circuit-Families-4spp - Lecture 16:...

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1 Lecture 16: Circuit Families Dynamic Logic Dynamic Noise Dynamic Keepers Dynamic Logic Dynamic gates uses a clocked pMOS pullup Two modes: precharge and evaluate 1 2 AY 4/3 2/3 A Y 1 1 A Y Static Pseudo-nMOS Dynamic Precharge Evaluate Y Precharge Footed vs Unfooted What if pulldown network is ON during precharge? Use series evaluation transistor to prevent fight. Y inputs Y inputs footed unfooted ff Inverter NAND2 NOR2 1 1 A Y 2 2 1 B A Y AB 1 1 1 g d = 1/3 p d = 2/3 g d = 2/3 p d = 3/3 g d = 1/3 p d = 3/3 Y footed unfooted 2 1 A Y 3 3 1 B A Y 2 2 1 g d = 2/3 p d = 3/3 g d = 3/3 p d = 4/3 g d = 2/3 p d = 5/3 Y 3 2 2 A Y foot precharge transistor Monotonicity Dynamic gates require monotonically rising inputs during evaluation, produce monotonically falling outputs Illegal for one dynamic gate to drive another! Precharge Evaluate Y Precharge A Output should rise but does not violates monotonicity during evaluation A A X Y
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EEL6323-S10-HLec016-Circuit-Families-4spp - Lecture 16:...

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