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EEL6323-S10-HLec020-Clock-Distribution-4spp - Lecture 20...

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1 Lecture 20: Clock Distribution Clock distribution trends Distribution networks Clock Power Clock Skew Timing Definitions Source: Ch 7 – J. Rabaey notes, Weste and Harris Notes, S. Russu, ISSCC, Clocking Synchronous systems use a clock to keep operations in sequence – Distinguish this from previous or next – Determine speed at which machine operates Clock must be distributed to all the sequencing elements – Flip-flops and latches – Domino circuits and memories On practical chips, the RC delay of the wire resistance and gate load is very long – Variations in this delay cause clock to get to different elements at different times – This is called clock skew Clock definition and parameters Skew – Spatial variation of the clock signal as distributed throughout the chip – Global vs. local skew Clock Jitter – Temporal variation of the clock with respect to a reference edge Duty Cycle Variation – 50/50 Design target
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  • Spring '08
  • Bashirullah
  • Clock signal, Clock distribution network, Jitter, DEC Alpha, Clock Distribution, Clock Distribution Networks

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EEL6323-S10-HLec020-Clock-Distribution-4spp - Lecture 20...

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