EEL6323-S10-HLec021-Sequencing-4spp

EEL6323-S10-HLec021-Sequencing-4spp - Lecture 21:...

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1 Lecture 21: Sequential Circuits Sequencing Elements Simple Latch/FF Timing Definitions Source: Ch 7 (W&H) Sequencing Use flip-flops to delay fast tokens so they move through exactly one stage each cycle. Inevitably adds some delay to the slow tokens Sequencing overhead Combinational logic – output depends on current inputs Sequential logic – output depends on current and previous inputs – Called state or tokens – Ex: FSM, pipeline CL clk in out clk clk clk CL CL Pipeline Finite State Machine Sequencing Elements Latch : Level sensitive – a.k.a. Flip-flop : edge triggered – a.k.a. Timing Diagrams D Flop Latch Q clk clk DQ clk D Q (latch) Q (flop) Latch Design Pass Transistor Latch Pros + + Cons Used in 1970’s
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2 Latch Design Transmission gate + - Inverting buffer + + + DQ D X Q Latch Design Tristate feedback + Buffered input + + Q D X Q D X Latch Design Buffered output + Widely used in standard cells + Q D X Flip-Flop Design Flip-flop is built as pair of back-to-back latches X D X Q Q
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3 Reset Force output low when reset asserted Synchronous vs. asynchronous D Q Q reset D Q D reset Q D reset reset reset Synchronous Reset Asynchronous Reset Symbol Flop DQ Latch reset reset
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This note was uploaded on 01/17/2011 for the course EEL 6323 taught by Professor Bashirullah during the Spring '08 term at University of Florida.

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EEL6323-S10-HLec021-Sequencing-4spp - Lecture 21:...

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