EEL6323-S10-HLec022-Sequencing-4spp

EEL6323-S10-HLec022- - Lecture 22 Sequential Circuits Setup and Hold time MS FF Power PC Pulsed FF HLFF SDFF SAFF Review Timing Definitions TCQ

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1 Lecture 22: Sequential Circuits Setup and Hold time MS FF – Power PC Pulsed FF – HLFF, SDFF, SAFF Source: Ch 7 – J. Rabaey notes, Weste and Harris Notes Review: Timing Definitions T CQ : Propagation Delay from Ck to Q, assuming D has been set early enough relative to Ck T setup (U): minimum time between D change and the transparency Ck Edge, such that Q will be guaranteed to change T hold : minimum time D must be held after the triggering Clk edge T skew : spatial variation of clock arrival time between two points in the chip t CLK t D t c 2 q t hold t su t Q DATA STABLE DATA STABLE Register CLK DQ FF/Latch Design Balancing act – Power, area, speed Look for similarities in FF/Latch design Input stage output stage Internal Node D Q X Data Storage Internal Node – Stores sampled data. How? Static: stores as long as power is on Dynamic: store data in a capacitor (internal node capacitance)
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2 Sampling D How do you sample data? Sampling should occur for
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This note was uploaded on 01/17/2011 for the course EEL 6323 taught by Professor Bashirullah during the Spring '08 term at University of Florida.

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EEL6323-S10-HLec022- - Lecture 22 Sequential Circuits Setup and Hold time MS FF Power PC Pulsed FF HLFF SDFF SAFF Review Timing Definitions TCQ

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