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Unformatted text preview: Problem 10.27 Find a two-level NOR implementation for a fundamental mode asynchronous sequential circuit with two inputs ( x 1 , x 2 ) and one output ( z ) that satisfies the following conditions: first, z is always zero when x 2 = 1. The output z changes to logic-1 on the first 0 1 transition of x 1 when x 2 = 0, and remains at logic-1 until x 2 goes to logic-1 and forces z back to logic-0. Step 1 : Interpret the specification As was evidenced by the struggle that we had with modeling this specification, this is an important step. Here is what we know for certain: Whenever x 2 = 1, z must be zero. The specific transition that causes z to change from zero to 1 is x 1 x 2 : 00 10. The specification categorizes the transition that causes the output to be asserted as the first 0 to 1 transition of x 1 when x 2 = 0. Out difficulty yesterday involves the question of whether this means the first and only the first , or whether it doesnt. Its not so clear what the specification means if it doesnt mean the first and only the first, because in that regard, it now depends on what the definition of first is. As I suggested with no small amount of chagrin yesterday in my e-mail, the published solution shows that after the output z returns to zero, every 0 to 1 transition of x 1 when x 2 = 0 causes z to change from zero to one. I recognized that the intent is to simplify the problem, but based on what I presented in lecture yesterday, it goes against what I think the specification should mean. With that said, I will present a model based on the more rigorous assumption, and one based on the less restrictive (but denotatively incorrect) idea presented in the solutions manual. Step 2 : Model the state machine Ill start with the model based on the rigorous reading of the specification. Since the notion of whether or not the first 00 10 transition has occurred is a piece of information that must be used to differentiate between states, we will use it as a piece of state information along with the output. This sets up a situation that I mentioned in class yesterday, namely, that two states with the same outputs could exist, if a different piece of state information described each one. Its possible (and likely, in fact) that the primitive flow table will show two different stable states in the same column that have output 0: one where the very first 00 10 transition has already happened, and another where it hasnt. With this in mind, we start by creating an initial state. Well call it state 1, and well assume that it is stable in the case where neither input is applied. Well also assume that z starts at zero, but this isnt a stretch given the statement in the specification detailing when z changes from zero to 1. In addition to stating that the output of state 1 is zero, we must also indicate the other applicable piece of state information. Clearly, in the initial state, the first 00 10 has not happened yet. happened yet....
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