Circuit Organization in Logic Works

Circuit Organization in Logic Works - For those of you with...

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For those of you with questions that you still haven’t asked: 1. What should the letters and numbers look like when they are shown on the display? a g dot a g dot a g dot a g dot a g dot a g dot a g dot a g dot Remember that you’re using the part called 7-Seg Disp Inv . Look in the Simulation IO library, or use the search feature to find it. 2. Where are the flip-flops? What are those extra inputs? D C S R Q Q You may use individual flip-flops and individual gates. Look in the Simulation Gates and Simulation Logic libraries. In class, I talked about a situation where a sequential device is restored to some initial state. The S and R inputs are not the inputs of an SR flip-flop. They are asynchronous inputs that the designer uses to control the initial state of the flip-flop. When you assert the S input, the flip-flop’s output state goes to logic-1 regardless of what else is going on. This happens without a clock pulse. Similarly, when you assert the R input, the flip-flop’s output state goes to logic-0 regardless of what else is going on. This happens without a clock pulse. Notice the bubbles on these inputs. They indicate that the inputs are active-low . This means that they do their jobs when they receive inputs of logic-0. This might seem backwards: to turn these inputs on, we have to provide a low logic signal instead of a high logic signal. However, this is the way that the flip-flops are designed to work. In addition, the inputs operate continuously. If you wanted to reset the flip-flop’s state, you would assert the R input by taking its input to logic-0. Before you could continue, you would have to take the R input back to logic-1. The flip-flops would stay at their reset level, however. Here’s a picture of that happening: D C S R Q Q +5V 0 1 0 1 0 1 1 D C S R Q Q +5V 0 1 0 1 0 1 0 D C S R Q Q +5V 0 1 0 1 0 1 0
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Notice that I have connected the S input to logic-1. Since the inputs have to go to logic-0 to do their jobs, the S input will never do its job, since it will never receive a low logic signal. In the first picture, the flip-flop has an output state of logic-1. Notice that the R input is being maintained at logic-1. When we switch the R-input to logic-0, the output state is reset. This is shown in the second picture.
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This note was uploaded on 01/17/2011 for the course ECE 3504 at Virginia Tech.

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Circuit Organization in Logic Works - For those of you with...

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