I1 Iterative Design - The Shift Register

I1 Iterative Design - The Shift Register - Iterative...

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Iterative Design: A First Approach Whether or not you know it, each of you has engaged in no fewer than two instances of iterative design during the course of taking ECE 2504. Of course, if everyone remembered and understood the design process in the specific context in which we will study it, there would be no need for this discussion. This document will place the iterative design process in terms of a device whose general operation should be familiar to you: the bidirectional shift register with parallel load. Hopefully, this development will place you in a better position to consider the analysis and design of other circuits that are derived iteratively. The Device We can consider the shift register in terms of its functions. In truth, every iterative design considers the operation of an output in the general terms of its functions, so the consideration of the shift register in this fashion will not represent a departure from the iterative design process as we will study it. The shift register consists of some number of state outputs. Imagine these states to be the outputs of D flip- flops. On the one hand, we will develop the equations for four such state outputs, without loss of generality. But more importantly, the method that we will use to develop these four state outputs would apply equally to a design containing any number of state outputs. This is based on the assumption that all of the state outputs operate in exactly the same fashion, and differ only in their position. Therefore, if we can complete the design of a general equation describing one arbitrary output, we can then iterate that equation over the range of precision required by the output set, considering boundary conditions where appropriate. With this in mind, let’s consider the inputs of the shift register: Since the register is a sequential device, it will have as many state inputs as there are state outputs. We will design a shift register having two mode select inputs, S 1 and S 0 . We can show a function table that describes what the shift register does for a specific combination of S 1 and S 0 : S 1 S 0 Function? 0 0 No State Change 0 1 Right Shift 1 0 Left Shift 1 1 Parallel Load The functions described by the mode select inputs imply the need for other inputs. In the case of a right shift, we need a value to fill the most significant bit. We will create a new input, a right serial input , so called because it fills the most significant bit on a right-shift. Similarly, we will need a left serial input to fill the least significant bit on a left-shift. On a parallel load, all of the states will need new values. Therefore, we need one parallel load input for each state output. Designing the Shift Register – The Traditional Approach
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I1 Iterative Design - The Shift Register - Iterative...

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