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ch09_solutions

# ch09_solutions - CHAPTER 9 9.1 V IC 2 0.995 F IEE = exp BE...

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Unformatted text preview: CHAPTER 9 9.1 V IC 2 0.995 F IEE = exp BE VBE = 0.025 ln = 0.132V IC1 0.005 F IEE VT (a) v I = VREF + VBE = -1.25 + 0.132 = -1.12 V vI = VREF + VBE = -1.25 - 0.132 = -1.38 V (b) v I = VREF + VBE = -2.00 + 0.132 = -1.87 V vI = VREF + VBE = -2.00 - 0.132 = -2.13 V 9.2 Since V REF = -1.25V, and v I = -1.6V, Q1 is off and Q 2 is conducting. vC1 = 0 V and v C2 = - F I EE RC -I EE RC = -(2mA)(350) = -0.700 V 9.3 Since V REF = -2V, and v I = -1.6V, Q2 is off and Q 1 is conducting. vC2 = 0 V and v C1 = - F I EE RC -I EE RC = -(5mA)(350) = -1.75 V Note that Q1 is beginning to enter the saturation region of operation, but VBC = +0.15 V is not really enough to turn on the collector-base diode. (See Problems 9.5 or 5.72.) 9.4 v I = VREF + 0.3V Q1 on; Q 2 off. I C1 = F I EE I EE = 0.3mA | I C2 = 0 vC1 = 0 - IC1(R1 + RC ) = -0.3mA(3.33k + 2k) = -1.60 V vC 2 = 0 - IC1R1 = -0.3mA(3.33k) = -0.999 V 9.5 With VBE = 0.7 and VBC = 0.3, the transis tor is technically in the saturation region, but calculating the currents using the transport model in Eq. (5.13) yields F = F 0.98 R 0.2 = = 49 | R = = = 0.25 1- F 1- 0.98 1- R 1- 0.2 -15 0.7 0.3 10-15 0.3 iC =10 exp - exp - -1 = 1.446 mA exp 0.025 0.25 0.025 0.025 0.7 0.3 10-15 0.7 iE =10-15exp - exp + -1 = 1.476 mA exp 0.025 49 0.025 0.025 10-15 0.7 10-15 0.3 iB = -1 + -1 = 29.52 A exp exp 49 0.025 0.25 0.025 At 0.3 V, the collector-base junction is not heavily forward-biased compared to the base-emitter junction, and IC = 48.99I B F I B . The transistor still acts as if it is operating in the forward-active region. 9-271 9.6 (a) For Q2 off, VH = 0 V. For Q2 on, IC IE and IE = -0.2 - 0.7 - (-2) =100 A 1.1x104 VL -4000I E = -0.400 V (b) Yes, these voltages are symmetrically positioned above and below VREF, i. e. VREF 0.2 V, and the current will be fully switched. See Parts (d) and (e). (c) For v I = 0 V, IC I E = 0 - 0.7 - (-2) =118 A 1.1x10 4 R= 0.4V = 3.39 k 118A (d) Q2 is cutoff. Q1 is saturated with VBC = +0.4 V. (e) Q1 is cutoff. Q2 is saturated with VBC = +0.2 V. (f) 0.2 V and 0.4 V are not large enough to heavily saturate Q1 or Q2 . Although the transistors are technically operating in the saturation region, the transistors still behave as if they are in the forward-active region. (See problem 9.5). 9.7 -0.2 - 0.7 - (-2) = 100 A | VL -4000IE = -0.400 V 1.1x10 4 0 - 0.7 - (-2) 0.4V For v I = VH = 0V, IC I E = = 118 A | R = = 3.39 k 4 1.1x10 118A 100A + 118A P = 2V = 218 W 2 R 11k R 4 k R 3.39k ' ' = 2.20 k | RC1 = C1 = = 800 | RC 2 = C 2 = = 678 (b) R'EE = EE = 5 5 5 5 5 5 (a) For v I = VL , I E = 9.8 V H = 0 - VBE = -0.7 V | VL = -( 1mA)(600) - 0.7 = -1.30 V VREF = V H + VL = -1.0 V 2 | V = (1mA)(600) = 0.600 V 9.9 V H = 0 - VBE = -0.7 V | VL = -(5mA)(200) - 0.7 = -1.70 V VREF = V H + VL = -1.2 V 2 | V = (5mA)(200) = 1 V 9.10 IEE = 5(0.3mA) = 1.5 mA | I 3 = I4 = 5(0.1mA) = 0.5 mA | RC = 2k = 400 5 9.11 9-272 V 0.8V = = 2.67 k | VH = 0 -VBE = -0.7 V | VL = -0.8 -VBE = -1.5 V IEE 0.3mA V + VL VREF = H = -1.10 V 2 V 0.8 0.8 V -1 = 0.289 V (b) NM H = NML = - VT 1+ ln -1 = - 0.025V 1+ ln 0.025 2 VT 2 (a) RC = (c) For Q1: VCB = -0.8 - (-0.7) = -0.1 V which represents a slight forward bias, but it is not enough to turn on the diode. For Q2: VCB = -0.8 - (-1.10) = +0.3 V which represents a reverse bias. Both values are satisfactory for operation of the logic gate. 9.12 (b) For Q1 on and Q 2 off, I C1 = F I EE IEE = 0.3mA | I C2 = 0 VL = 0 - IC1(R1 + RC ) - 0.7V = -0.3mA(3.33k + 2k) - 0.7V = -2.30 V V H = 0 - IC1R1 - 0.7V = -0.3mA(3.33k) - 0.7 = -1.70 V V = V H -VL = 0.600 V VH + VL = -2.0V = VREF | Yes, the input and output voltage levels are 2 compatible with each other and are symmetrically placed around V REF. (c ) R 1 R R C C Q 3 v Q 4 v O1 O2 vI 0.1 mA Q 1 Q 2 VREF 0.1 mA I - 5.2 V EE 9-273 9.13 (a) See Prob. 9.12 (b) V = F I EE RC I EE RC V H = 0 - F I EE R1 - VBE VREF = 0.4V = 200 2mA -IEE R1 -VBE = -2mA(600) - 0.7V = -1.90 V | RC = VL = 0 - F IEE (R1 + RC ) - VBE -I EE (R1 + RC ) -VBE = -2mA(800) - 0.7V = -2.30 V V H + VL -1.90 - 2.30 = = -2.10 V 2 2 9.14 V = VBE + iB 4 RC | Let the Fanout = N; F = 35. Then there will be N base I currents that must be supplied from emitter - follower transistor Q 4 : iE4 = N EE F + 1 I I + IC 4 I + IE 4 I EE VBE = VT ln C 4 = VT ln E 4 = VT ln 1 + E 4 = 0.025ln 1+ N IC 4 IE 4 IE 4 (F + 1)I E 4 i E4 I EE iB 4 = =N 2 F + 1 (F + 1) 0.3mA 0.3mA V = VBE + iB 4 RC = 0.025 ln1+ N + N 2 2k | V 0.025 36(0.1mA) (36) 3N 0.6N 0.025 = 0.025ln 1 + | Using MATLAB or HP - Solver : N 13.4 N =13 + 36 (36)2 9.15 ' RC1 = ' REE RC1 1850 R 2000 ' = = 185 | RC 2 = C 2 = = 200 10 10 10 10 R 11.7k R 42k = EE = =1.17 k | R' = = = 4.20 k 10 10 10 10 9.16 V = F I EE RC I EE RC = 0.2mA(2k) = 0.400 V VH = 0 - F I EE R1 - VBE -IEE R1 -VBE = -0.2mA(2k) - 0.7V = -1.10 V VREF = VL = 0 - F I EE (R1 + RC ) - VBE -IEE (R1 + RC ) - VBE = -0.2mA(4 k) - 0.7V = -1.50 V VH + VL -1.10 -1.50 = = -1.30 V 2 2 V 0.4 0.4 V NM L = NM H = - VT 1 + ln -1 = - 0.025V 1+ ln -1 = 0.107 V 2 0.025 VT 2 [V - (-2)]+ [VL - (-2)] = (4 -1.10 -1.50)V = 28.0 A IE 3 + I E 4 = H R 50k P = 28A(2V ) + 0.2mA(5.2V ) = 1.10 mW 9-274 9.17 V V V - VT 1+ ln -1 | 0.1V = - 0.025V [ ln (40V -1)] 1+ 2 2 VT Solving by trial - and - error, HP - Solver, or MATLAB : V = 0.383 V NM H = function f=dv15(v) f=4-20*v+1+log(40*v-1); fzero('dv15',0.5) yields ans = 0.3831 9.18 (a ) The change in v BE will be neglected : v BE = VT ln 0.8IC = -5.6mV IC V H = 0 - VBE = 0 - 0.7 = -0.7 V - no change VL has dropped by 0.12V. | V = 0.3mA(1.2)(2k) = 0.72 V NM H = NM L = VL = 0 - F I EE RC - VBE -I EE RC - VBE = -0.3mA( )(2k) - 0.7V = -1.42 V 1.2 V 0.72 0.72 V - VT 1 + ln -1 = - 0.025V 1+ ln -1 = 0.252 V 2 2 0.025 VT (b) At node A : V H = 0 - VBE = 0 - 0.7 = -0.7 V - no change -1.0 - 0.7 - (-5.2) V (1.2)(2k) - 0.7V = -1.30 V 1.2(11.7k) VL = 0 - F I EE RC - VBE -I EE RC - VBE = - VL also has not changed! are set by resistor ratios. NMH = NML = 9.19 | Similar results hold at node B because the voltages V 0.6 0.6 V - VT 1 + ln -1 = - 0.025V 1+ ln -1 = 0.197 V, unchanged 2 0.025 VT 2 ' ' RC1 = 10RC1 = 10(1.85k) = 18.5 k | RC 2 = 10RC 2 = 10(2k) = 20.0 k ' REE = 10REE = 10(11.7k) = 117 k | R' = 10R =10(42k) = 420 k 9-275 9.20 (a) VH REE = = -0.7V | V = 0.8V | VL = -0.8 - 0.7 = -1.5V | VREF = -1.1 - 0.7 - (-5.2) V 0.8V = 11.3 k | RC 2 = = 2.67 k 0.3 mA 0.3mA -0.7 - 0.7 - (-5.2) V 0.8V IE1 = = 0.336mA | RC1 = = 2.38 k 11.3 k 0.336mA 0.8 0.8 -1 = 0.289 V (b) NM H = NML = - 0.025V 1+ ln 0.025 2 V H + VL = -1.1V 2 (c ) VCB1 = -0.8 - (-0.7) = -0.1V | VCB 2 = -0.8 - (-1.1) = +0.3V The collector - base junction of Q 2 is reverse - biased by 0.3 V. Although the collector - base junction of Q 1 is forward - biased by 0.1 V, this is not large enough to cause a problem. Therefore the voltages are acceptable. 9.21 NM H = V V -VT 1 + ln -1 2 VT V V - 0.025V 1 + ln -1 V = 0.383V 2 0.025 For room temperature, VT = 0.025V : 0.1V = For - 55C, VT = 0.0188V : 0.1V = For + 75C, VT = 0.0300V : 0.1V = V = 0.413 V 9.22 V V - 0.0188V 1+ ln -1 V = 0.346V 2 0.0188 V V - 0.0300V 1+ ln -1 V = 0.413V 0.0300 2 In the original circuit : VH = -2mA(2k) - 0.7V = -1.1V | V = 2mA(2k) = 0.4V VREF. VL = -1.1V - V = -1.5V . V H and VL are symmetrically placed about REE = -1.3 - 0.7 - (-5.2) V =16.0 k. R1 and R C2 remain unchanged. 0.2 mA -1.1- 0.7 - (-5.2) V For Q1 on and and Q 2 off : I EE = = 0.2125mA 16.0 k VL1 = -(0.2125mA)(2k + RC1) - 0.7V | VL1 = -1.5V RC1 =1.77 k. Note that there are only 3 variables Thus we cannot force them all to the desired level. For this design, (R1, RC1 and R C2 ) and four voltage levels. V H 2 = -(0.2125mA)(2k) - 0.7V = -1.125V rather than the desired - 1.10V 9-276 9.23 VEQ = 60k (-5.2V ) = -3.0V | REQ = 60k 44k = 25.38k 60k + 44k -3.0 - 0.7 - (-5.2) V -3.0 - 0.7 - (-5.2) V IBS = | IEE = F I BS = F 25.38 + (F + 1)30 k 25.38 + ( F + 1)30 k -3.0 - 0.7 - (-5.2) V = 50.0 A | Active region operation 30 k 0V | VCBS = VREF - VBE 2 - VBS = VREF - 0.7V - (-3V ) For large F , I EE = requires V CBS VREF - 0.7V - (-3V ) 0 VREF -2.30 V 9.24 - 0.7 = -2.2V 200A Design choice - Choose VB = -3V | I B = = 4A 50 V -VEE -3 - (-5.2) RE = B = =10.8 k RE =11 k IE 0.204mA The base of Q S must not be higher than V L Choose I R2 = 20A. R 2 = 0 - (-3) =150 k R2 =150 k 20A -3 - (-5.2) =138 k R1 =136 k 16A IR1 = IR 2 - I B = 16A. R1 = 9.25 ' ' RC1 = 5RC1 = 5(1.85k) = 9.25 k | RC 2 = 5RC 2 = 5(2k) = 10.0 k ' REE = 5REE = 5( 11.7k) = 58.5 k | R' = 5R = 5(42k) = 210 k 9.26 RC Q 3 Q A B C D 2 V REF Y=A+B+C+D I EE R -V EE 9.27 9-277 RC Q 4 Q A B C D E 2 V REF Y =A+B+C+D+E I EE R -V EE 9.28 -0.7 - (-3.2) = 2.98 mA 840 VL =1.3V - (2.98mA)(390) - 0.7V = -0.56 V (a) For Q4 on, IC 4 = F I E 4 I E 4 = For Q 4 off, and neglecting the base current in Q 0.6 - 0.7 - (-3.2) = 3.69 mA 840 V 1.16V V = 0.60 - (-0.56) =1.16V | R = = = 314 IC 2 3.69mA 5 , V H 1.3 - 0.7 = +0.60 V (b) For v A = 0.6V, IC 2 = F I E 2 I E 2 = 9.29 -0.7 - (-2.5) = 2.14 mA 840 VL =1.0V - (2.14mA)(390) - 0.7V = -0.540 V (a ) For Q 4 on, IC 4 = F IE 4 I E 4 = For Q 4 off, and neglecting the base current in Q 0.3 - 0.7 - (-2.5) = 2.50 mA 840 V 0.84V V = 0.30 - (-0.54 ) = 0.84V | R = = = 336 IC 2 2.50mA 5 , V H = 1.0 - 0.7 = +0.300 V (b) For v A = 0.3V, IC 2 = F IE 2 IE 2 = 9-278 9.30 V CC 390 A Q 2 B Q 3 Q 4 Q 5 Y=A+B 840 600 (a) -V EE (b) The NOR output is taken from the collectors of Q2 /Q3 , and the 390- resistor, Q5, and the 600- resistor are removed. 9.31 min vO = -IEE RL = -(2.5mA)(1.2k) = -3.00 V | I E = I EE + VBC = 4 - 5 = -1 V , so the transistor is in the forward I 5.25mA IB = E = = 0.103 mA and IC = F IB = 5.15 mA. F + 1 50 + 1 9.32 (a-b) See Problem 9.33 (c) IEE vO 4 - 0.7 = 2.5mA + = 5.25 mA RL 1.2k - active region. - (VI - 0.7)V 1k = 3.7V = 3.7 mA 1k Circuit 9.32-Transient-1 Time +1.500m (s) 9.33 Simulation Results from B2SPICE (V) +0.000e+000 +500.000u +1.000m +2.000m +3.000 +2.000 +1.000 +0.000e+000 -1.000 -2.000 -3.000 -4.000 IEE = 4 mA V(1) V(3) 9-279 Circuit 9.32-Transient-2 (V) +0.000e+000 +500.000u +1.000m +1.500m Time (s) +2.000m +3.000 +2.000 +1.000 +0.000e+000 -1.000 -2.000 -3.000 IEE = 2 mA 9.34 V(1) V(3) (a) vO = v I - 0.7V = (-1.7 + sin 2000t) V min (b) vO = -2.7V 2.7V = 0.13 mA with no safety margin. 20k The transistor will cut off at the bottom of the input waveform for I EE = 0.13 mA. | - I EE RL -2.7V I EE 9.35 Simulation results from B2SPICE Circuit 9.35-Transient-1 (V) +0.000e+000 +500.000u +1.000m +1.500m Time (s) +2.000m +0.000e+000 -500.000m -1.000 -1.500 -2.000 -2.500 -3.000 V(1) V(3) 9.36 (a ) The transistor cuts off for v min O = -I EE RL = -(0.5mA )(1k) = -0.5V. So v I -0.5 +0.7 = +0.2V. For v O > 1.5 V, the transistor enters the saturation region of operation. Therefore : 0.2 V vI 1.5 V . 2.2V min = 2.2 mA (b) vO = -1.5 - 0.7 = -2.2 V . We need - I EE RL -2.2V I EE 1k 9.37 min vO = -10 - 0.7 = -10.7 V . We need - I EE RL -10.7V I EE 10.7V =10.7 mA 1k 9-280 9.38 Assuming Q 1 off and using voltage division, IE = -12 = -15 12 - (-15) 12 + = 60 mA ! 2000 500 2000 RE = 500 2000 + RE 9.39 min (a) vO = -10 - 0.7 = -10.7 V . 4.7k We need -15V -10.7V 4.7k + RE | IE = v I - 0.7 v I - 0.7 - VEE + RL RE RE (15 -10.7)(4.7k) = 1.89 k 10.7 (b) I E = 9.40 -0.7 -0.7 - (-15) + = 7.43 mA | 4700 1890 (c ) IE = -10 - 0.7 -10 - 0.7 - (-15) + = 0 mA 4700 1890 (a) See the solution to Problem 9.41. (b) vO = v I - 0.7V = (-2.2 +1.5 sin 2000t ) V max (c ) v Imax = -1.5 +1.5 = 0V | vO = -0.7V | v v -VEE -0.7 -0.7 - (-6) I = O + O | I max = + = 3.93 mA E RL RE E 4700 1300 -3.7 -3.7 - (-6) + = 0.982 mA 4700 1300 4.7k 4.7k(6 - 3.7) = 2920 (e ) We need - 6V -3.7V RE 3.7 4.7k + RE (d ) max min v O = -2.2 -1.5 = -3.7V | I E = 9.41 Simulation results from B2SPICE Circuit 9.37-Transient-2 +0.000e+000 +500.000u +1.000m +1.500m +2.000m +2.500m Time (s) +3.000m +0.000e+000 -1.000 -2.000 -3.000 -4.000 V(1) V(3) V(5) 9-281 9.42 The outputs act as a " wired - or" connection. For v I = -0.7V, vO1 = vO 2 = -0.7 V | IE 3 = 0 | IE 4 = 0.1mA + 0.1mA = 0.200 mA For v I = -1.3V , vO1 = v O 2 = -0.7 V | I E 3 = 0.1mA + 0.1mA = 0.200 mA | I E 4 = 0 9.43 Y = A+ B | Z = A + B 9.44 Use the circuits in Prob. 9.30 A OR B Y C NOR D 9.45 5.6 k R Q 5 1 R Q 5 EQ 5.28 k - 0.3 V V VREF 91 k R 2 EQ + _ R VREF - 0.301 V R 3 3 42 k 42 k - 5.2 V 0.1 mA - 5.2 V v REF = -0.301 - 5280iB 5 - v BE 5 -0.301- v BE5 v E 2 = v REF - v BE 2 -0.301- v BE 5 - v BE 2 v E 2 - (-5.2) 4.90 - v BE5 - v BE 2 4.90 - 0.7 - 0.7 = = = 0.299 mA 11700 11700 11700 For a temperature increase of 50 o C, v BE = 50 o C( -1.8mV / o C) = -0.090V iE 2 = iE 2 = 4.90 - 0.610 - 0.610 = 0.315 mA - a 5.4% increase. 11700 9-282 9.46 R EQ Q5 6.07 k VEQ V REF + _ - 0.301 V R3 48.3 k - 5.2 V VREF = -0.301 - 6070i B 5 - v BE 5 Neglecting the small variations in iB 5 and v BE 5, VREF is essentially unchanged. Since REE, RC 2 and R all change by the same factor, R V = VREE C does not change, REE and VH , VL , NM H , and NM L all remain unchanged. 9.47 For large F , VREF = -0.301- 5280i B 5 - v BE 5 -0.301- v BE 5 = At 25 oC, v BE 5 = 0.7V and VREF = -1.00V 1.8mV (a) T = +60C | v BE5 = 60C - = -0.108V | VREF = -0.892V C 1.8mV (b) T = -80C | v BE 5 = -80C- = +0.144V | VREF = -1.14V C Note: A more exact calculation yields the same answers. 9.48 *PROBLEM 9.48 - ECL INVERTER VTC VIN 2 0 DC -1.3 VREF 4 0 -1.0 VEE 8 0 -5.2 Q1 1 2 3 NBJT Q2 5 4 3 NBJT Q3 0 1 6 NBJT Q4 0 5 7 NBJT REE 3 8 11.7K RC1 0 1 1.85K RC2 0 5 2K R3 6 8 42K R4 7 8 42K .DC VIN -1.3 -0.7 .01 .TEMP -55 25 85 .MODEL NBJT NPN BF=40 BR=0.25 VA=50 .PROBE V(2) V(1) V(5) V(6) V(7) .PRINT DC V(2) V(6) V(7) .END 9-283 T VT VH VL V VREF VIH VOH VIL VOL NMH NML -55C 0.0188 V -0.846 V -1.40 V 0.554 V -1.00 V -0.918 V -0.865 V -1.08 V -1.38 V 0.053 V 0.300 V +25C 0.0257 V -0.724 V -1.30 V 0.576 V -1.00 V -0.895 V -0.750 V -1.10 V -1.27 V 0.145 V 0.170 V +85C 0.0309 V -0.629 V -1.22 V 0.591 V -1.00 V -0.880 V -0.660 V -1.12 V -1.19 V 0.220 V 0.070 V VIH , VOH , VOL , and VIL were calculated from Eqns. 9.29 - 9.32. With a fixed reference voltage, the noise margins change with temperature and can become zero for a large enough temperature change. 9.49 *PROBLEM 9.49 - ECL INVERTER VTC WITH REFERENCE VIN 2 0 DC -1.3 VEE 8 0 -5.2 Q1 1 2 3 NBJT Q2 5 4 3 NBJT Q3 0 1 6 NBJT Q4 0 5 7 NBJT REE 3 8 11.7K RC1 0 1 1.85K RC2 0 5 2K R3 6 8 42K R4 7 8 42K Q5 0 9 4 NBJT R1 0 9 5.6K R2 9 8 91K RE 4 8 42K .OP .DC VIN -1.3 -0.7 .01 .TEMP -55 25 85 .MODEL NBJT NPN BF=40 BR=0.25 VA=50 IS=1FA .PROBE V(4) V(3) V(2) V(1) V(5) V(6) V(7) .PRINT DC V(4) V(3) V(2) V(6) V(7) .END 9-284 T VT VH VL V VREF VIH VOH VIL VOL NMH NML -55C 0.0188 V -0.803 V -1.35 V 0.547 V -1.11 V -1.03 V -0.784 V -1.19 V -1.33 V 0.246 V 0.140 V +25C 0.0257 V -0.665 V -1.25 V 0.585 V -0.975 V -0.870 V -0.639 V -1.08 V -1.22 V 0.231 V 0.140 V +85C 0.0309 V -0.558 V -1.18 V 0.622 V -0.869 V -0.747 V -0.527 V -0.991 V -1.15 V 0.220 V 0.160 V VIH , VOH , VOL , and VIL were calculated from Eqns. 9.29 - 9.32. With a simple temperature dependent reference voltage, VREF stays near the middle of the voltage swing, and the noise margin variation with temperature is significantly reduced. 9.50 -2 - (-5.2) V 0.1mA = 32 k ( 33 k for a discrete design.) | I B 5 = = 2.44A 0.100 mA 40 + 1 -1.3 - (-5.2) Choose I R2 10IB 5 25A | R2 = = 156 k (160 k for a discrete design.) 25A R3 = IR1 25A + IB 5 27.4A | R1 = 0 - (-1.3) = 47.4 k ( 47 k for a discrete design.) 27.4A 9.51 0, 1, 2, or 3 base currents may be drawn out of the reference depending on the state of each logic gate. Each unit of base current results in a drop 0.3mA V = I BR = (2.7k) = 0.026V . VREF = -1- NV for N = 0, 1, 2, 3 yields : F + 1 VREF = -1 V, - 0.974 V, - 0.948 V, - 0.922 V ??? 0, 1, 2, 3, or 4 base currents may be drawn out of the reference depending on the state of each logic gate. The Thevenin equivalent of the bias circuit is (neglecting the small - signal resistance of the diode) VEQ = -5.2V + 0.3mA(11.7k) + 0.7V = -0.990V and REQ = 11.7k Each unit of base current results in a drop V = I BR = 0.3mA (11.7k) = 0.113V . F +1 VREF = -0.990 - NV for N = 0, 1, 2, 3, 4 yields : VREF = -0.990 V, - 0.877 V, - 0.764 V , - 0.651 V, - 0.538 V 9-285 ??? v v I v iC = I S exp BE - exp BC + S exp BC -1 VT R VT VT v v I v iE = I S exp BE - exp BC + S exp BE -1 VT F VT VT v BE > 4VT and v BC < -4VT v 1 v BE I S v BE iC I S exp BE and iE = I S 1+ exp exp = iC Fi E F VT F VT VT i i v BE VT ln C = VT ln F E IS IS 9.54 ISD = 9.55 IS 1 fA = = 1.02 fA F 0.98 assume V A = . BE Both transistors are in the forward - active region. For simplicity, I = IC1 + IB1 + I B 2 | Since the transistors are identical and have the same V IC 2 = IC1 and IB1 = IB 2 | I = IC1 + 2IB1 = ( F + 2)I B1 | IC 2 = F IB 2 = F IB1 IC 2 = 9.56 , F 25 I= 25A | IC 2 = 23.2 A | See the current mirror in Chapter 5. F + 2 25 + 2 For Fig. 9.32, P 0.5mA (5.2V) = 2.6mW = 2600W . For 20W, the power must be reduced by 130X. The currents must be reduced by 130X and the resistors must increase by this factor to keep the logic swing the same : R C = 130(2k) = 260k. Using Eq. (9.54), P = 0.69(260k)(2 pF ) = 359 ns - rather slow! 9.57 RC 2k = =1k | V = 0.3mA(1k) = 0.3V | VH = 0 - 0.7 = -0.7V 2 2 -0.7 -1.0 VL = VH - 0.3V = -1.0V | VREF = V = -0.850 V | P 0.5mA(5.2V ) = 2.6mW 2 P = 0.69(1k)(2 pF ) = 1.38ns | PDP = 2.6mW (1.38ns) = 3.59 pJ ' RC = 9-286 9.58 V = 0.15mA(2k) = 0.3V | VH = 0 - 0.7 = -0.7V -0.7 -1.0 V = -0.850 V | P 0.25mA(5.2V ) = 1.30mW 2 P = 0.69(2k)(2 pF ) = 2.76ns | PDP = 1.30mW (2.76ns) = 3.59 pJ VL = VH - 0.3V = -1.0V | VREF = 9.59 V V = 2(0 - 0.7 - (-1)) = 0.6V 2 VL = VH - V = 0 - .6 = -0.600 V . Ignoring the base currents, the average power is (-1.7 - (-3.3)) V (-1.0 - (-3.3))V P + 3.3V = 5.67 mW 1.6k 3.2k V 0.6 V 0.6 RC 2 = = = 600 | RC1 = = = 505 I EE 2 -1- 0.7 - (-3.3) I EE1 -0.7 - 0.7 - (-3.3) 1600 1600 (b) Y = A + B + C Y = A + B + C (c) 5 versus 6 transistors (a) At the outputs : VH = 0 V | VREF = VH - 0.7 - 9.60 At the outputs : VH = 0 V | VL = VH - V = 0 - .4 = -0.400 V . At the base of Q D : V H VBD = 0 - 0.7 = -0.7V | VL VBD = -0.4 - 0.7 = -1.10V VREF = -0.7 -1.1 = -0.90V | VEE VREF - 0.7 - 0.6 = -0.9 - 0.7 - 0.6 = -2.20 V 2 For VEE = -2.20V : RB = RE = RC1 = -0.9 - (-2.2) V = 1.30 k 1 mA [-0.9 - 0.7 - (-2.2)]+ [-0.7 - 0.7 - (-2.2)] V 2 1 mA = 700 0.4V 0.4V = 350 | RC 2 = = 467 -0.7 - 0.7 - (-2.2) -0.9 - 0.7 - (-2.2) A A 700 700 RC1 0 4 505 RC2 0 5 600 .OP .TRAN 0.1N 30N .MODEL NBJT NPN BF=40 BR=0.25 +IS=5E-16 TF =0.15NS TR=15NS +CJC=0.5PF CJE=.25PF CJS=1.0PF +RB=100 RC=5 RE=1 .PROBE V(2) V(1) V(4) V(5) V(6) .END 9.61 *PROBLEM 9.61 - ECL DELAY VIN 1 0 PULSE(-0.6 0 0 .01NS .01NS 15NS) VB 8 0 -0.6 VREF 6 0 -1.0 VEE 7 0 -3.3 QA 0 1 2 NBJT QB 0 8 2 NBJT QC 0 8 2 NBJT QD 4 2 3 NBJT QE 5 6 3 NBJT RB 2 7 3.2K RE 3 7 1.6K 9-287 200mV Result: P = 0.95 ns 0V -200mV -400mV -600mV vI Time -800mV 0s 5ns 10ns 15ns 20ns 25ns 30ns 9.62 One approach is to scale all the resistor values. To reduce the power from 2.7 mW to 1.0 mW, the resistor values should all be increased a factor of 2.7. RC1 = 2.7(1.85k) = 5.00 k | RC 2 = 2.7(2k) = 5.40 k REE = 2.7(11.7k) = 31.6 k | R = 2.7(42k) = 113 k 9.63 Voltage levels remain unchanged REE = : VREF = -1V , VH = -0.7V, VL = -1.3V , I EE = 0.3mA -1 - 0.7 - (-2) V 0.6V 0.6V = 1 k | RC1 = = = 1 k -0.7 - 0.7 - (-2) 0.3 mA 0.6mA A 1 k -1 - (-2) V 0.3 + 0.6 I2 + mA = 0.650mA | P = 0.65mA(2V ) = 1.30 mW (-28%) 10 k 2 Note that this gate will now have quite asymmetrical delays at the two outputs since the two collector resistors differ by a factor of two in value. 9.64 The circuit is the pnp version of the ECL gate in Fig. 9.100. 9.65 | Y = ABC VL = 0 | V H = VL + V = +0.6V | VREF = 0.7 +1.3 1mW = +1.0V | I = = 333A 2 3V (1 +0.7) + (0.7 + 0.7) = 1.55V The average voltage at the emitter of Q D is 2 (3 -1.55)V = 4.84 k | R = (3 -1)V = 60.1 k | R = 0.6V = 2.23 k RE = B C 0.9(333A) 0.1(333A) (3 -1.7)V 4.84 k 9-288 9.66 *Problem 9.66(a) - PNP ECL GATE DELAY VI 4 0 PULSE(0.6 0 0 .01NS .01NS 25NS) VB 7 0 DC 0.6 VREF 6 0 DC 1.0 VEE 1 0 DC 3 QA 0 4 3 PBJT QB 0 7 3 PBJT QC 0 7 3 PBJT QD 0 3 2 PBJT QE 5 6 2 PBJT RB 1 3 60.1K RE 1 2 4.84K RC 5 0 2.23K .OP .TRAN 0.1N 50N .MODEL PBJT PNP BF=40 BR=0.25 IS=5E-16 +TF =0.15NS TR=15NS +CJC=0.5PF CJE=.25PF CJS=1.0PF +RB=100 RC=5 RE=1 .PROBE V(4) V(3) V(5) .END 800mV 600mV vI 400mV 200mV vO 0V Time -200mV 0s 10ns 20ns 30ns 40ns 50ns Result: P = 6.0ns. This delay is dominated by a slow charge up at the base of QD. *Problem 9.66(b) - Fig. 9.91 VIN 1 0 PULSE( -2.3 -1.7 0 .01NS .01NS 15NS) VREF 6 0 -2.0 IEE 2 0 0.0003 Q1 3 1 2 NBJT Q2 4 6 2 NBJT R1 0 5 3.33K RC1 5 3 2K RC2 5 4 2K .OP .TRAN 0.1N 30N .MODEL NBJT NPN BF=40 BR=0.25 IS=5E-16 TF =0.15NS TR=15NS +CJC=0.5PF CJE=.25PF CJS=1.0PF RB=100 RC=5 RE=1 .PROBE V(1) V(3) V(4) .END Result: P = 2.4 ns. *Problem 9.66(c) - Fig. 9.93 VIN 1 0 PULSE( -1.5 -1.1 0 .01NS .01NS 15NS) VREF 6 0 DC -1.30 IEE 2 0 DC 0.0002 Q1 3 1 2 NBJT Q2 4 6 2 NBJT Q3 0 3 7 NBJT Q4 0 4 8 NBJT R1 0 5 2K RC1 5 3 2K RC2 5 4 2K RE1 7 9 50K RE2 8 9 50K VEE 9 0 DC -2 9-289 .OP .TRAN 0.1N 30N .MODEL NBJT NPN BF=40 BR=0.25 IS=1E-17 TF =0.15NS TR=15NS +CJC=0.5PF CJE=.25PF CJS=1.0PF RB=100 RC=5 RE=1 .PROBE V(1) V(3) V(4) V(7) V(8) .END Result: P = 3.0 ns. 9.67 Applying the transport model, V V I V IC = I S exp BE - exp BC - S exp BC -1 VT R VT VT I V I V IB = S exp BE -1 + S exp BC -1 F VT R VT 0.2 -4.8 10-15 -4.8 IC =10-15exp exp - exp - -1 = 2.98 pA 0.025 0.25 0.025 0.025 10-15 0.2 10-15 -4.8 IB = -1 + -1 = 74.5 fA exp exp 40 0.025 0.25 0.025 Although the transistor is technically in the forward-active region, (and operating with IC = F IB), it is esentially off - its terminal currents are zero for most practical purposes. 9.68 1 For IC = 0, VCESAT = VT ln R 1+ IC (R + 1)I B = V T I 1- C F IB 1 ln R + 1 1.25 VCESAT = VT ln R = 0.025 ln = 0.402 V 0.25 R 9.69 (a) For the Transport model with VBE = VBC, the transport current iT = 0: IC = I S VBC I V I 40 =160 exp -1 and I E = S exp BE -1 C = F = R VT F VT I E R 0.25 v BE = VB - 0.6 | v BC = VB - 0.8 = v BE - 0.2 (b) v v I v iE = I S exp BE - exp BC + S exp BE -1 VT VT F VT v v -0.2 IS v BE iE = I S exp BE - exp BE exp -1 + exp VT VT VT F VT v I v 1 v I v iE I S exp BE + S exp BE = I S 1+ exp BE = S exp BE VT F VT VT F VT F 9-290 -- --- v v -0.2 I S v BE - 0.2 iC = I S exp BE - exp BE exp -1 - exp VT VT VT R VT v i 40 iC I S exp BE | C = F = = 0.976 VT iE 41 iC = -1 iB = i E - iC = 2i E | Both junctions will be forward - biased. Neglect iE I v I v v v I v the - 1 terms : S exp BE + S exp BC = 2IS exp BE - exp BC + 2 S exp BE F VT R VT VT VT F VT 1 1 2+ 2+ R 0.25 = 27.2mV v BE - v BC = VT ln = 0.025V ln 1 1 2+ 2+ F 40 (c ) (v B - v I ) - (v B - 0.8) = 27.7mV 9.70 (a) For the default value of F = 40, | v I = 0.773 V -3 IC = F IB Forward - active region | VBE VT ln IC 10 A = 0.025V ln -15 = 0.691 V IS 10 A (b) IC < F I B saturation region; VBE is given by Eqn. 5.45 1 IB + IC I B + (1- R )IC R + 1 VBE = VT ln = V ln 1 T 1 1 I S + (1- R ) IS + F F R +1 1 -3 25x10-6 + 10 0.25 + 1 VBE = 0.025V ln = 0.691 V 1 -15 1 10 + 80 0.25 + 1 1 -3 10-3 + 10 0.25 +1 = 0.710 V (c ) IC < F I B saturation region | VBE = 0.025V ln 1 -15 1 10 + 40 0.25 + 1 9-291 9.71 R = R 2 I 1mA = | C = = 40 R +1 3 I B 25A 1 = VT ln R 1+ IC 40 3 1+ (R + 1)I B = 0.025V ln 3 =117 mV ( ) 40 IC 2 1- 1- F IB 50 (a) VCESAT (b) VCESAT 9.72 40 3 1 + 3 = 89.5 mV = (0.025V )ln 40 2 1 - 100 R = R 1 I 1mA = | C = = 40 R + 1 2 I B 25A 1 = VT ln R 1+ IC (R + 1)I B = 0.025V ln ( ) I 1- C F IB 40 3 1+ 2 40 = 114 mV 2 1 - 60 (a) VCESAT I 1mA = 25 | VCESAT = (0.025V )ln (b) C = I B 40A 9.73 25 3 1+ 2 25 = 88.7 mV 2 1- 60 R = R 0.25 = = 0.2 R +1 1.25 V 0.2V (a ) = exp CESAT = exp = 2980 0.025V VT 40 1+ F 1+ 0.25 2980 I R I ( ) = IC = C IB C 1 F 1- 1 40 1 - 37.9 0.2(2980) R I 1 5 - 0.2 IB C = = 63.3 A FOR 37.9 2k (b) = exp VCESAT 0.1V = 54.6 = exp 0.025V VT 40 1+ F 1 + 0.25 54.6 I R I ( ) = IC = C IB C 1 F 1 - 1 40 1- 9.25 0.2(54.6) R I 1 5 - 0.1 IB C = = 265 A FOR 9.25 2k 9-292 9.74 R = V 0.1V = exp CESAT = exp = 54.6 0.025V VT 40 F 1+ I 1+ 0.25(54.6) I I R = C = C IB C 1 F 1- 1 40 1 - 9.25 0.2(54.6) R I 1 5 - 0.1 IB C = = 147 A FOR 9.25 3.6k R 0.25 = = 0.2 R +1 1.25 9.75 1 + 1 1.25 For IC = 0, VCESAT = VT ln = VT ln R = 0.025ln = 40.2 mV 0.25 R R 1 + 1 41 For IE = 0, VECSAT = VT ln = VT ln F = 0.025ln = 0.617 mV 40 F F F 40 R 0.25 = = 0.976 R = = = 0.200 F +1 41 R + 1 1.25 1- 0.976(0.2) = 3.40ns iCMAX 5V = 2.5 mA 2k 9.76 F = S = 0.976(0.4ns + 0.2(12ns)) t S = (3.40ns)ln 2mA - (-0.5mA) = 5.07 ns 2.5mA - (-0.5mA) 40 9.77 V H = VCC = 3.0 V VL = VCESAT = 0.15 VIL = 0.7 - VCESAT = 0.7 - 0.04V = 0.66V VIH VBESAT 2 = 0.8 V 3 - 0.7 - 0.8 V v I = 3V : IB1 = = 375A | I B 2 =1.25IB1 = 469A 4 k 3 - 0.8 - 0.15 V 3 - 0.15 v I = 0.15V : IIL = - = -513A | IC 2SAT = A = 1.43mA 4 k 2000 1.43mA + N (513A) 40(469A) N 33.8 N 33. v I = VH : I = v I = VL : I = 5 - 0.7 - 0.8 5 - 0.15 + = 4.13mA | P = 5(4.13mA) = 20.6 mW (0.8)4k (0.8)2k 5 - 0.8 - 0.15 = 0.844mA | P = 5(0.844mA) = 4.22 mW (1.2)4k 9.78 Pmax = 20.6 mW | Pmin = 4.22 mW 9-293 9.79 1 Using Eqs. 9.55 and 9.58 : VCC - iC RC = VT ln R 1+ 1+ iC ( R +1)iB i 1- C F iB iC 1 1.25(1.09mA) 5 - 2000iC = 0.025ln iC = 2.4659 mA iC .2 1- 40(1.09mA) vCESAT = 5 - 2000iC = 0.0682V 9.80 V H = 2.5 V | VL = VCESAT = 0.15 V VIL = 0.7 - VCESAT = 0.55V | VOL VL = 0.15V VIH VBESAT 2 = 0.8 V | VOH V H = 2.5 V NML = 0.55 - 0.15 = 0.40 V NM H = 2.5 - 0.8 = 1.7 V 9.81 For v I = VH , we require VCC = VBE 2SAT + VBC1 + I B1RB = 0.8 + 0.7 + V =1.5V + V where V is the voltage across the base resistor. V must be large enough to abosorb VBE process variations and to establish the base current. 0.5 V should be sufficient. Thus VCC = 2.0 V or more is acceptable. 9.82 The VTC transitions are set by the values of vBE and v BESAT and are not changed by the power supply voltage. (b) VIL = 0.66 V and VIH = 0.80 V. But VOH VH = 3 V and VOL VL = 0.15 V. (c) NM H = 3 - 0.8 = 2.2 V | NM L = 0.66-0.15 = 0.51 V. We need to reduce the currents by a factor of 11.2. Thus RB = 11.2 (4k) = 44.8 k and RC = 11.2 (2k) = 22.4 k 9.83 9.84 (a) *Problem 9.84 - Prototype TTL Inverter +Delay VI 1 0 DC 0 PWL(0 0 0.2N 5 25N 5 25.2N 0 +50N 0) VCC 5 0 DC 5 Q1 3 2 1 NBJT Q2 4 3 0 NBJT RB 5 2 4K RC 5 4 2K *RB 5 2 45.2K *RC 5 4 22.6K .OP .TRAN .1N 80N .MODEL NBJT NPN BF=40 BR=0.25 +IS=5E-16 TF =0.15NS TR=15NS +CJC=0.5PF CJE=.25PF CJS=1.0PF +RB=100 RC=5 RE=1 .PROBE V(1) V(2) V(3) V(4) .END 9-294 (a) 6.0V vI 4.0V 2.0V vO 0V Time -2.0V 0s 20ns 40ns 60ns 80ns Results: (a) P = 2.9 ns 9.85 (b) P = 15.8 ns. (a) V H = 5V | VL = VCE 2 SAT = 0.15V 5 - 0.15 - 0.6 v I = VL = 0.15V , I IN = - = -1.06 mA 4000 v I = VH = 5V, IIN = -IS 0 where I S is the diode saturation current. (b) (c) 9.86 5 - 0.8 - 0.6 5 - 0.15 = 0.90mA; + N (1.06mA) 40(0.9mA); N 31. 4000 2000 -1.06 mA compared to -1.01 mA and 0 mA compared to 0.22 mA. IB = If we assume that the diode on-voltage is 0.7 V to match the base-emitter voltage of the BJT, then the VTC will be the same as that in Fig. 9.47, and both VTCs will be the same. 295 9.87 *Figure 9.106 - Prototype TTL Inverter VTC's VI 1 0 DC 0 VCC 5 0 DC 5 *DTL D1A 6 1 D1 D2A 6 7 D1 RBA 5 6 4K RCA 5 8 2K Q2A 8 7 0 NBJT *TTL Q1B 3 2 1 NBJT Q2B 4 3 0 NBJT RBB 5 2 4K RCB 5 4 2K .DC VI 0 5 .01 .MODEL NBJT NPN BF=40 BR=0.25 IS=5E-16 TF =0.15NS TR=15NS +CJC=0.5PF CJE=.25PF CJS=1.0PF RB=100 RC=5 RE=1 .MODEL D1 D IS=5E-16 TT=0.15NS CJO=1PF .PROBE V(1) V(2) V(3) V(4) V(6) V(7) V(8) .END 9.88 *Figure 9.106 - Prototype Inverter Delays VI 1 0 DC 0 PWL(0 0 0.2N 5 25N 5 25.2N 0 5 50N 0) VCC 5 0 DC 5 *DTL D1A 6 1 D1 D2A 6 7 D1 RBA 5 6 4K RCA 5 8 2K Q2A 8 7 0 NBJT *TTL Q1B 3 2 1 NBJT Q2B 4 3 0 NBJT RBB 5 2 4K RCB 5 4 2K .OP .TRAN 0.1N 100N .MODEL NBJT NPN BF=40 BR=0.25 IS=5E-16 TF =0.15NS TR=15NS +CJC=0.5PF CJE=.25PF CJS=1.0PF RB=100 RC=5 RE=1 .MODEL D1 D IS=5E-16 TT=0.15NS CJO=1PF .PROBE V(1) V(2) V(3) V(4) V(6) V(7) V(8) .END 5.0V 4.0V vO 3.0V 2.0V 1.0V 0V 0V 1.0V 2.0V vI 3.0V 4.0V 5.0V The TTL transition is sharper (more abrupt) and is shifted by approximately 50 mV. 6.0V vI 4.0V vO TTL 2.0V vO DTL 0V Time -2.0V 0s 20ns 40ns 60ns 80ns 100ns The fall time of the output of the TTL gate is somewhat slower than the DTL gate since transistor Q1 must come out of saturation. However, the rise time of the DTL gate is extremely slow because there is no reverse base current to remove the charge from the transistor base. 9-296 9.89 *Figure 9.107 - DTL Inverter Delays VI 1 0 DC 0 PWL(0 0 0.2N 5 25N 5 25.2N 0 50N 0) VCC 5 0 DC 5 *DTLA D1A 6 1 D1 D2A 6 7 D1 RBA 5 6 4K RCA 5 8 2K Q2A 8 7 0 NBJT *DTL-B D1B 2 1 D1 D2B 2 3 D1 Q2B 4 3 0 NBJT RBB 5 2 4K RCB 5 4 2K RB1 3 0 1K .OP .TRAN 0.1N 100N .MODEL NBJT NPN BF=40 BR=0.25 IS=5E-16 TF =0.15NS TR=15NS +CJC=0.5PF CJE=.25PF CJS=1.0PF RB=100 RC=5 RE=1 .MODEL D1 D IS=5E-16 TT=0.15NS CJO=1PF .PROBE V(1) V(2) V(3) V(4) V(6) V(7) V(8) .END 6.0V vO (b) 4.0V vI 2.0V vO (a) 0V Time -2.0V 0s 20ns 40ns 60ns 80ns 100ns Without the 1-k resistor, the rise time of the DTL gate is extremely slow because there is no reverse base current to remove the charge from the transistor base. The resistor provides an initial reverse base current of -0.7 mA to turn off the transistor and significantly reduces the rise time and propagation delay. 9.90 See problem 9.91. 9.91 *Figure 9.108 - Inverter VTC VI 1 0 DC 0 VCC 6 0 DC 3.3 Q1 3 2 1 NBJT Q2 5 3 4 NBJT Q3 5 4 0 NBJT R1 6 2 4K R2 6 5 2K R3 4 0 3K .OP .DC VI 0 3.3 0.01 .MODEL NBJT NPN BF=40 BR=0.25 IS=1E-16 TF =0.15NS TR=15NS +CJC=0.5PF CJE=.25PF CJS=1.0PF RB=100 RC=5 RE=1 .PROBE V(1) V(2) V(3) V(4) V(5) .END The first break point occurs when the input reaches a voltage large enough to just start turning on Q2 , at approximately V CESAT1 + V BE2 = 0.04V + 0.6 V = 0.64V. The second breakpoint begins when the input reaches VCESAT1 + VBE2 +VBE3 = 0.04V + 0.7 + 0.6 V = 1.34V. Note that the shallow slope is set by the ratio of R2 /R3 = 2/3, and also note that Q3 cannot saturate. From the B2SPICE simulation, VH = 3.3 V, VL VBE3 + VCESAT2 = 0.82V, VIH = 1.38 V, VOL = 0.84 V, VIL = 1.38 V, VOH = 2.82 V. NM H = 2.82 1.38 = 1.54 V. NM L = 1.38 - 0.84 = 0.54 V. Circuit 9.108-DC Transfer-1 +1.50 VO (V) +0.00e+000 +500.00m +1.00 +2.00 +2.50 +3.00 +3.50 +3.00 +2.50 +2.00 +1.50 +1.00 +500.00m +0.00e+000 V(2) V(7) VI 9.92 297 V CC = 5 V 4 k iR 2k 0.875 mA N(0.875 mA) iC = 0 vH < 5 V N VL 0.15 V Q1 Q2 + 0.19 V "Off" 0.875 mA From the analysis in the text, iB1 = we see that the fanout is limited by the V H condition. 5 - 0.7 - 0.8 V = 0.875mA | i E1 = - Ri B1 = -0.875mA 4 k 5 - 2000(N )( 0.875x10-3 ) 1.5 N 2 Fanout = 2 9.93 V CC = 5 V 1.2(4 k ) 1.2(2k ) 1.5 V i B1 + 0.7 V VH iIH = RiB1 Q1 N (R + 1)i B1 Q2 + 0.8 V 1.2(2k ) + 0.15 V - From the analysis in the text, we see that the fanout is limited by the V H condition. 5 - 0.7 - 0.8 V iB1 = = 0.729mA | i E1 = - Ri B1 = -0.25(0.729mA) = 0.182mA 4(1.2) k 5 - 2000(1.2)(N )( 0.182x10-3 ) 1.5 N 8.01 Fanout = 8 iB1 = 5 - 0.7 - 0.8 V =1.09mA | i E1 = -R iB1 = -0.25( 1.09mA) = 0.273mA 4 (0.8) k 5 - 2000(0.8)(N )(0.273x10-3 ) 1.5 N 8.01 Fanout = 8 The result is independent of the tolerance if the resistors track each other. Note that Eq. 9.83 also yields N = 8 if more digits are used in the calculation. 9.94 9-298 From the analysis in the text, we see that the fanout is limited by the V H condition. 5 - 0.7 - 0.8 5 - 0.7 - 0.8 iB1 = | iE1 = - R iB1 = -0.25i B1 | 5 - 2000(N )(0.25) 1.5 RB 5 k RB RB 9.95 (a) Q4 is in the forward - active region with IE = ( F + 1)I B IE =101 5 - 0.7 - 0.6 = 234 mA 1600 (b) Q4 saturates; IE = I B + IC = 9.96 5 - 0.8 - 0.6 5 - 0.6 - 0.15 + = 34.9 mA 1600 130 (a) PD = 5V (234mA) = 1.17 W (b) PD = 5V (34.9mA) = 0.175 W .DC IL 0 30MA 0.01MA .MODEL NBJT NPN BF=40 BR=0.25 IS=5E-16 TF =0.15NS TR=15NS +CJC=0.5PF CJE=.25PF CJS=1.0PF RB=100 RC=5 RE=1 .MODEL D1 D IS=5E-16 .PROBE V(1) V(2) V(3) V(4) .END 9.97 *Figure 9.109 - TTL Output Current VCC 5 0 DC 5 RB 5 3 1.6K RS 5 4 130 Q1 4 3 2 NBJT D1 2 1 D1 IL 1 0 DC 0 5.0V vO 4.0V 3.0V 2.0V iL 1.0V 0A 5mA 10mA 15mA 20mA 25mA 30mA 299 9.98 *Problem 9.98 - Modified TTL Inverter VTC VI 1 0 DC 0 VCC 9 0 DC 5 Q1 2 8 1 NBJT Q2 4 3 0 NBJT Q3 6 2 3 NBJT Q4 7 6 5 NBJT D1 5 4 DN RB 9 8 4K RC 9 6 1.6K RS 9 7 130 RL 4 0 100K Q5 10 11 0 NBJT RB5 3 11 3K RC5 3 10 1K .DC VI 0 5 .01 .MODEL NBJT NPN BF=40 BR=0.25 IS=1E-17 TF =0.25NS TR=25NS +CJC=0.6PF CJE=.6PF CJS=1.25PF RB=100 RC=5 RE=1 .MODEL DN D .PROBE V(1) V(2) V(3) V(4) V(5) V(6) .END 9.99 4.0V vO 3.0V 2.0V 1.0V 0V 0V 1.0V 2.0V vI 3.0V 4.0V 5.0V In the modified TTL circuit, Q3 cannot start conducting until its base reaches at lease VBE5 + VBE6 = 1.2 V. + 5V 20 k 8 k + Q 0.7 V + 0.8 V 1 Q 3 Q + 5 k 0.8 V 2 (a) v I = V H : Q4 off - I B 4 = 0 = IC 4 | Q2 saturated with IC 4 = 0 (5 - 0.7 - 0.8 - 0.8)V =135 A | I = - I = -0.25 135 A = -33.8 A IB1 = ( ) E1 R B1 20k IC1 = -169 A | IC 3 = (5 - 0.15 - 0.8)V 8k = 506 A 0.8V = 515 A 5k IE 3 = 506A +169A = 675 A | I B 2 = 675A - 9-300 (b) v I = VL : Q2,Q3 off ; Q4 on (5 - 0.8 - 0.15)V = 203 A = I I = B1 20k E1 | IC1 = 0 9.100 9.101 See Problem 9.101. 4.0V *Problem 10.85 - Low Power TTL Inverter VTC versus Temperature VI 1 0 DC 0 VCC 9 0 DC 5 Q1 2 8 1 NBJT Q2 4 3 0 NBJT Q3 6 2 3 NBJT Q4 7 6 5 NBJT D1 5 4 DN RB 9 8 20K RC 9 6 8K RS 9 7 650 RL 4 0 100K RE 3 0 5K .DC VI 0 5 .01 .TEMP -55 25 85 .MODEL NBJT NPN BF=40 BR=0.25 IS=1E-17 TF =0.25NS TR=25NS +CJC=0.6PF CJE=.6PF CJS=1.25PF RB=100 RC=5 RE=1 .MODEL DN D .PROBE V(1) V(2) V(3) V(4) V(5) V(6) .END 9.102 +5V RC RS 130 vO 3.0V 2.0V -55 o C 1.0V +25 o C +85 o C 0V 0V 1.0V 2.0V vI 3.0V 4.0V 5.0V 1.6 k Q4 V H = 5 - 0.7 - 0.7 - N x 0.17 mA N(I IH ) RC F + 1 N (0.17mA) (1600) 40 + 1 V H 2.4V N 180 V H = 3.6 - 301 9.103 For small R , fanout is limited by the iB 3 = ( R +1)iB1 = 1.05 = 567A 5k (5 - 0.15 - 0.8)V + 567A - 0.8V =1.95mA iB 2 = iE 3 - iRE = 2k 1.25k (5 - 0.8 - 0.15)V = 0.810mA | = R = 0.05 = 0.0476 iIL = -iE1 = -i B1 = R 5k 1+ R 1.05 1 1- 0.15V 0.0476(403.4 ) Using Eq. 9.61, = exp = 9.52 = 403.4 FOR = 20 20 1 0.025V 1+ 0.05 403.4 N (0.810mA) 9.52(1.95mA) N = 22 9.104 For the vO = VL case, the equations are given in Problem 9.103. For v O = VH , function [N,X]=P9104 br=0; bf=40; g=exp(.15/.025); for i=1:50 br=br+.1; ar=br/(1+br); ib3=(1+br)*675; ib2=1730+ib3; bfor=40*(1-1/(ar*g))/(1+bf/(br*g)); N1=fix(bfor*ib2/1013); N2=1.2*(bf+1)*4000/(2.7*br*1600); N(i)=min(N1,N2); X(i)=0.1*i; end [Y,X]=p9104; plot(X,Y) (5 - 0.7 - 0.8 - 0.8)V vO = VL case (v I = V H ). V H = 5 - I B 4 RC - 0.7 - 0.7 2.4V 5 - 0.7 - 0.8 - 0.8 2.7 IIH = R = R 4000 4000 NIIH N R 2.7 IB 4 = = F + 1 F + 1 4000 N 1.2( F + 1)(4000) 2.7R (1600) 100 80 Fanout 60 40 20 0 0 1 2 3 4 5 Inverse Current Gain 9-302 9.105 +2 V 2 k +2 V + 2k 0.8 V 2k 0.8 V 0.15 V + Q1 Q2 + VH i IN Q1 0.7 V + 0.8 V "Saturated" Q3 (a) VH = 2 - VECSAT 2 = 2 - 0.15 =1.85 V | VL = VCESAT 3 = 0.15 V iB 2 0 | i IH = 0.25 (b) iIH : = 62.5 A 2k (2 - 0.8 - 0.15)V - (2 - 0.8 - 0.8 - 0.15)V = -650 A iIL = -i B1 = - 2k 2k (c ) Assume FOR 28.3 For the pnp transistor : N(62.5A) 28.3 N = 56 2k (2 - 0.7 - 0.8)V N = 13 For the npn transistor : N(650A) 28.3(1.25) 2k 9.106 (2 - 0.7 - 0.8)V (2 - 0.8 - 0.8 - 0.15)V (a) VL = VCESAT 3 = 0.15 V (b) v I = 0.15V : | VH = 2 - VBE2 = 2 - 0.7 = 1.3 V 2 - 0.8 - 0.15 2 - 0.15 - 0.15 iIL = -(iB1 + iC1 ) = - + = -247 A 10000 12000 2 - 0.7 - 0.8 v I = 1.3V : i IL = R iB1 = 0.25 = 12.5 A 104 2 - 0.8 - 0.15 2 - 0.15 - 0.15 + =1.875mA (c ) Using FOR = 28.3 : iL = iB 2 + iC 2 = 6000 1000 2 - 0.7 - 0.8 2 - 0.8 iB 3 = + 1.25 = 162.5A 12000 10000 28.3(0.1625mA) N (0.247mA) + 1.875mA N = 11 9.107 (a) Y = ABC (b) VL = VCESAT 3 = 0.15 V (c ) v I = 1.9V , input diode is off and | VH = 3.3 - VBE1 - VD = 3.3 -1.4 = 1.9 V 3.3 - 0.7 - 0.15 = -408 A 6000 iIH = 0. v I = 0.15V, i IL = - 303 2.0V vO 1.5V 1.0V 0.5V The VTC starts to decrease immediately because Q2 is ready to conduct due to the 0.7 V drop across the input diode. When the input has increased to approximately 0.7 V, Q begins to conduct and the 3 output drops rapidly. The VTC is much sloppier than that of the corresponding TTL gate. For this particular circuit VIL = 0 and VIH = 0.8 V. Based upon our definitions, NM L = 0. However, the initial slope can be reduced by changing the ratio RC/R2 so that VIL = 0.7 V. vI 1.0V 2.0V 3.0V 4.0V 0V 0V 9.108 (a) If either input A is low or input B is low, VB2 will be low. Q2 will be off, Q3 will be on and Y will be low. Therefore Y = A + B Y = AB . +5 V +5 V 4k 4 k 0.8 V +0.3 V 0.15 V + 10 k -5 V 10 k 5 k + +0.45 V +4.3 V Q1 VB Q2 -5 V (b) VH = 5 - IB 5R2 - VBE5 5 - VBE 5 = 5 - 0.7 = 4.30 V VL = 5 - F I E 3R2 - I B 5 R2 - VBE 5 5 - I E 3R2 -VBE 5 +0.7 - 0.7 - (-5) =1.00mA | VL = 5 - 0.001(4000) - 0.7 = +0.300 V 5000 5 - 0.7 -VB VB - (-5) VB - 0.7 - (-5) 1 + VB =1.97V = (c ) v I = 4.3V : 1.25 4000 10000 5000 41 5 - 0.7 -1.97 IB1 = = 582 A | I E1 = -0.25IB1 = -146 A | I IH = 146 A 4000 0.3 + 0.15 - (-5) 5 - 0.8 - 0.3 v I = 0.3V : I B1 = = 975 A | IC1 = - = -545 A 4000 10000 IE1 = I B1 + IC1 = 430 A | I IL = -430 A IE 3 = 9-304 9.109 1.5 V 1.5 V 800 1k 800 1k 0.70 V 0.25 V - 0.45 V + Off Q 1 VH + 0.45 V + 0.7 V - Q 1 Off (a) VH = VCC = 1.5 V | VL = "VCESAT1"= 0.7 - 0.45 = 0.25 V (b) For v I = 1.5V , the input diode is off, and I IH = 0. 1.5 - 0.45 - 0.25 = 1.00 mA 800 (c ) Note that Q 1 operates as if it were in the forward - active region : For v I = 0.25V , I IL = 1.5 - 0.45 - 0.70 1.5 - 0.25 F IB1 NI IL + I R2 | 40 N = 16 N (0.001) + 800 1000 9.110 v BE + v D 2 - v D1 = vCE | For v D2 v D1, v CE = v BE = 0.7 V Note, the external base current source should be labeled i BB . iC = iCC + iD1 | iB = i BB - iD1 | iC = Fi B iCC + i D1 = F (iBB - iD1) i D1 = iD 2 F iBB - iCC 20(0.25) -1 = mA = 0.191 mA F + 1 21 = iBB - iD1 = 0.25 - 0.191 = 0.059 mA | iC = 20iB = 20iD 2 = 1.18 mA the collector - base junction of Q 1 is 9.111 In this circuit as drawn, iB1 = 9.112 bypassed by a Schottky diode. Q 1 will be " off" with VBC = +0.45 V . 5 - 0.45 - 0.7 = 963 A | I IN = 0 | i B 2 = i B1 = 963 A 4000 iB1 = 5 - 0.7 - 0.25 = 1.01 mA | I IN = -iB1 = -1.01 mA | iB 2 = 0 4000 9-305 9.113 For v I = 5V , the Schottky diode bypasses the collector - base junction, I IH 0, 5 - .45 - 0.7 and i B 2 = i B1 = = 963A. 4000 5 - 0.7 - 0.25 For v I = 0.25V, I IL = - = -1.01 mA. 4000 5 - 0.25 40(963A) N(1.01mA) + N = 35 2000 5 - 0.45 - 0.7 - 0.7 5 - 0.25 - 0.7 =1.13 mA | iC 3 = = 4.50 mA 2800 900 iE1 = 0 | iC1 = -iB 3 = -1.13 mA | iB1 = iB 3 =1.13 mA 0.7 - 0.25 1 iB 2 = iB 3 + iC 3 - (iC6 + i B 6 ) | (iC 6 + iB 6 ) = 1 + = 1.85 mA 250 40 iB 2 =1.13mA + 4.50mA -1.85mA = 3.78 mA | Q4 and Q5 are off . i B 3 = i RB = Q2,Q3,and Q6 are all off . Q4 is conducting only the small 5 - 0.7 - 0.25 = 1.45 mA 2800 9.114 (a) v I = VOH : (b) v I = VOL : leakage current of Q2 . iB1 = iRB = iE 5 = 9.115 4.0V 5 - 900iB 5 - 0.7 5 - 0.7 = 1.23 mA 3500 3500 4.0V vO vI 3.0V 3.0V 2.0V 2.0V vO 1.0V 1.0V Time 0V 0V 1.0V 2.0V vI 3.0V 4.0V 5.0V 0V 0s 5ns 10ns 15ns 20ns 25ns 30ns Result: P = 3.0 ns *Problem 9.115 - Schottky TTL Inverter VTC VI 1 0 DC 3.5 PWL(0 3.5 0.2N 0.25 15N 0.25 15.2N 3.5 30N 3.5) VCC 9 0 DC 5 9-306 Q1 2 8 1 NBJT D1 2 8 DS Q2 4 3 0 NBJT D2 3 4 DS Q3 6 2 3 NBJT D3 2 6 DS Q4 7 5 4 NBJT Q5 7 6 5 NBJT D5 6 7 DS RB 9 8 2.8K RC 9 6 900 RS 9 7 50 R5 5 0 3.5K RL 4 0 100K Q6 10 11 0 NBJT D6 11 10 DS R2 3 11 500 R6 3 10 250 .OP .DC VI 0 5 .01 .TRAN .025N 30N .MODEL NBJT NPN BF=40 BR=0.25 IS=1E-17 TF =0.15NS TR=15NS +CJC=1PF CJE=.5PF CJS=1PF RB=100 RC=10 RE=1 .MODEL DS D IS=1E-12 .PROBE V(1) V(2) V(3) V(4) V(5) V(6) .END 9.116 +5V 20 k 8 k 120 Off Q5 Off Q 4 VH D2 + Off 0.7 V - + D3 Off R5 4 k vO Q 2 0.25 V D4 Off R2 1.5 k Q6 - R6 3 k + + 0.25 V 0.7 V + + Q3 0.25 V - 0.7 V 9-307 (a) v I = V H : iB2 = Q 4 and Q 5 are off. 5 - 0.7 - 0.7 5 - 0.25 - 0.7 = 180 A | i C2 = = 506 A 20000 8000 0.7 - 0.25 1 iB3 = iB 2 + iC 2 - (iC 6 + i B 6 ) | (iC 6 + i B 6 ) = 1+ = 154 A 3000 40 iB3 = 180A + 506A -154A = 532 A (b) v I = VL : 9.117 Q2 ,Q 3,Q 4 ,Q 5 and Q 6 all have i C 0. *Problem 9.117 - Low Power Schottky TTL Inverter VTC VI 1 0 DC 3.5 PWL(0 3.5 0.2N 0.25 10N 0.25 10.2N 3.5 20n 3.5) VCC 9 0 DC 5 DS1 8 1 DS Q3 4 3 0 NBJT D3 3 4 DS Q2 6 8 3 NBJT D2 8 6 DS Q4 7 5 4 NBJT Q5 7 6 5 NBJT D5 6 7 DS DS3 5 6 DS DS4 4 6 DS RB 9 8 20K RC 9 6 8K RS 9 7 120 R5 5 4 4K Q6 10 11 0 NBJT D6 11 10 DS R2 3 11 1.5K R6 3 10 3K RL 4 0 100K .OP .DC VI 0 5 .01 .TRAN .025N 20N .TEMP -55 +25 +85 .MODEL NBJT NPN BF=40 BR=0.25 IS=1E-17 TF =0.25NS TR=25NS +CJC=0.6PF CJE=.6PF CJS=1.25PF RB=100 RC=5 RE=1 .MODEL DS D IS=1E-12 .PROBE V(1) V(2) V(3) V(4) V(5) V(6) .END 9-308 Result: P = 13 ns. Note that the delays are dependent upon the specific BJT models used in SPICE. 9.118 *Problem 9.118 - Advanced Low Power Schottky TTL Inverter VTC VI 1 0 DC 4 PWL(0 4 0.2N 0.3 125N 0.3 125.2N 4 150N 4) VCC 9 0 DC 5 Q4 0 1 2 PBJT R1 9 2 40K Q1 12 2 8 NBJT D1 2 12 DS R2 9 12 60K DS1 8 1 DS Q8 4 3 0 NBJT D8 3 4 DS Q6 6 8 3 NBJT D6 8 6 DS Q3 7 5 4 NBJT Q2 7 6 5 NBJT D2 6 7 DS DS3 4 6 DS R3 9 6 15K R4 9 7 50 R5 5 4 4K Q7 10 11 0 NBJT D7 11 10 DS R6 3 11 3K R7 3 10 6K RL 4 0 100K .OP *.DC VI 0 5 .01 .TRAN .05N 150N .TEMP -55 +25 +85 .MODEL NBJT NPN BF=40 BR=0.25 IS=1E-17 TF =0.15NS TR=15NS +CJC=1PF CJE=.5PF CJS=1PF RB=100 RC=10 RE=1 .MODEL PBJT PNP BF=40 BR=0.25 IS=1E-17 TF =0.15NS TR=15NS +CJC=1PF CJE=.5PF CJS=1PF RB=100 RC=10 RE=1 .MODEL DS D IS=1E-12 .PROBE V(1) V(3) V(4) V(5) V(6) 9-309 .END 5.0V 5.0V vO 4.0V 4.0V -55 o C 3.0V 3.0V vO +25 oC 2.0V 2.0V 1.0V 1.0V +85 o C vI Time 0V 0V 1.0V 2.0V 0V 0s vI 3.0V 4.0V 5.0V 50ns 100ns 150ns Result: P = 22 ns. Note that the delays are highly dependent upon the specific BJT models used in SPICE. 9.119 Y = A + B + C | VH = 0 V | VL = -540IC = -540 VREF - 0.7 - (-3) = -0.72(VREF + 2.3) 750 VH + VL = VREF - 0.7 + 0.4 + 0.7 = VREF + 0.4 2 0 - 0.72(VREF + 2.3) = VREF + 0.4 VREF = -0.903V | VL = -0.72(-.903 + 2.3) = -1.01 V 2 RC 0.54 k Y RC V REF- 0.4V 3.3 k Y C V REF + 0.7 V 0.75 k RE VREF V REF- 0.7V 2.4 k RE 9.119 -3 V 9.120 -3 V 9-310 9.120 Y = A + B + C | V H = 0 V | VL = VREF - 0.4 0 + (VREF - 0.4 ) VH + VL = VREF | = VREF VREF = -0.40 V | VL = -0.80V 2 2 9.121 The circuit can be modeled by a normal BJT with a Schottky diode in parallel with the collector base junction. If iC and iB are defined to be the collector- and base-currents of the BJT, iC + i B = 5 - 0.7 1.075mA = 1.075mA | iC Fi B iB = = 26.9 A | iC =1.05 mA 4000 40 +5 V i=0 4 k iC iB Q1 9.122 If we assume 50% of the gates are switching (an over estimate), (a) P = (b) PDP = (0.1mW )(0.1ns) =10 fJ (a) P = 50W = 2W /gate | P = 1ns | PDP = (2W )(1ns) = 2 fJ 0.5( 50x10 6 ) | The result in Part (a) is off the graph! 9.123 If we assume 50% of the gates are switching (an over estimate), (b) PDP = (0.1mW )(0.1ns) =10 fJ 9.124 100W =1W /gate | P = 0.25ns | PDP = (1W )(0.25ns) = 0.25 fJ 0.5( x10 6 ) 200 | The result in Part (a) is off the graph! (a) P = 9.125 PDP 0.5 pJ = = 1.67 ns P 0.3mW (b) P = | P = PDP 0.5 pJ = = 0.5 mW P 1ns PDP 28 pJ = = 2.8 ns P 10mW (a) PDP = (0.7ns)(40mW ) = 28 pJ (b) P = 9.126 PDP 28 pJ = = 140 mW P 0.2ns 9-311 (a) PDP = (10ns)(2mW ) = 20 pJ (b) P = 9.127 | P = PDP 20 pJ = = 4 ns P 5mW PDP 20 pJ = = 67 mW P 0.3ns Results from B2SPICE: VH = 4.48 V, VL = 0.54 V, PHL = 3.3 ns, PLH = 4.4 ns. Circuit 9_127-DC Transfer-2 (V) +5.000 +0.000e+000 +500.000m +1.000 +1.500 +2.000 +2.500 +3.000 +3.500 +4.000 +4.500 VI +4.000 +3.000 +2.000 +1.000 +0.000e+000 V(3) Circuit 9_127-Transient-2 (V) +5.000 +0.000e+000 +10.000n +20.000n +30.000n +40.000n +50.000n +60.000n +70.000n +80.000n +90.000n Time (s) +100.000n +4.000 +3.000 +2.000 +1.000 +0.000e+000 V(3) 9-312 9.128 V M A 4 DD B M3 Q 4 vI R B M 2 v O Q A M 1 3 9.129 V M A 4 DD B M 3 Q 4 v B M 2 O B A M 1 M 6 A M7 Q M 5 3 9.130 Results from B2SPICE with R = 4 k: VH = 5 V, VL = 0 V, PHL = 1.9 ns, PLH = 4.1 ns. Circuit 9_130-DC Transfer-1 (V) +0.000e+000 +500.000m +1.000 +1.500 +2.000 +2.500 +3.000 +3.500 +4.000 +4.500 VI +5.000 +4.000 +3.000 +2.000 +1.000 +0.000e+000 V(3) 9-313 Circuit 9_130-Transient-1 (V) +0.000e+000 +10.000n +20.000n +30.000n +40.000n +50.000n +60.000n +70.000n +80.000n +90.000n Time (s) +100.000n +5.000 +4.000 +3.000 +2.000 +1.000 +0.000e+000 V(3) 9.131 V A M 3 DD B M 4 Q M M B 4 A 2 1 R v O A M5 M6 B 9.132 VDD M3 M4 Q4 B M2 R vO A B A M1 B M6 A M5 9-314 9.133 Results from B2SPICE: VH = 4.7 V, VL = 0.34 V, PHL = 7.0 ns, PLH = 14 ns. Circuit 9_133-DC Transfer-4 (V) +5.000 +0.000e+000 +500.000m +1.000 +1.500 +2.000 +2.500 +3.000 +3.500 +4.000 +4.500 VI +4.000 +3.000 +2.000 +1.000 +0.000e+000 V(5) Circuit 9_133-Transient-4 (V) +5.000 +0.000e+000 +10.000n +20.000n +30.000n +40.000n +50.000n +60.000n +70.000n +80.000n +90.000n Time (s) +100.000n +4.000 +3.000 +2.000 +1.000 V(5) 9-315 ...
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ch09_solutions - CHAPTER 9 9.1 V IC 2 0.995 F IEE = exp BE...

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