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1
EE 101 Sample Midterm
Redekopp
Name:_________________________________________________________________
Score:
/ 100
1.
Short Answer
(5 pts.)
a.
What range of numbers can be represented with a 6
bit 2’s complement system?
b.
What are the three primary design goals that we try to optimize in circuit design?
c.
Given a 5to32 decoder with inputs (A4, A3, A2, A1, A0), write out the logic equation
for output 17 (i.e. O17)?
d.
NANDOR logic implementations degenerates to what gate?
e.
A 20to1 mux would require a minimum of how many select bits?
2.
For the decimal numbers below, convert to the indicated representation systems.
a.
(107)
10
= (?)
8bit
2’s comp.
= (?)
16
’s comp.
(i.e. just conv. 2’s comp. value to hex)
(4 pts.)
b.
(59)
10
= (?)
8bit signed magnitude
(2 pts.)
c.
235
10
= (?)
8
= (?)
BCD
(6 pts.)
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3.
Find the simplest SOP form of the following logic equation.
(8 pts.)
C
AB
C
C
A
B
C
A
F
]
)
(
)
[(
SingleVariable Theorems
(T1)
X + 0
= X
(T1’)
X • 1 = X
(Identities)
(T2)
X + 1 = 1
(T2’)
X • 0 = 0
(Null elements)
(T3)
X + X = X
(T3’)
X • X = X
(Idempotency)
(T4)
(X’)’ = X
(Involution)
(T5)
X + X’ = 1
(T5’)
X • X’ = 0
(Complement)
Two and ThreeVariable Theorems
(T6)
X +Y = Y + X
(T6’)
X • Y = Y • X
(Commutativity)
(T7)
(X+Y)+Z = X+(Y+Z)
(T7’)
(X•Y) •Z = X• (Y•Z)
(Associativity)
(T8)
X•(Y+Z) = X•Y +
X
•Z
(T8’)
X+(Y•Z) = (X+Y) • (
X+Z)
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 Fall '06
 Redekopp

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