SampleFinalSol

SampleFinalSol - EE 101 Sample Final Redekopp Name: _ 1.)...

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EE 101 Sample Final Redekopp Name: ________________________________________ Taken from Fall ’02 / ‘03 1.) Answer the following questions as True or False a.) A 4-to-1 multiplexer requires at least 4 select lines : true / false FALSE b.) An 8-to-1 mux and no other logic can be used to implement any combinational logic function of 4 input variables : true / false FALSE c.) A 3-to-8 decoder along with (4) 8-input OR gates can be used to implement any combinational logic involving 3 input variables and 4 output variables : true / false TRUE d.) 3 separate 2-to-1 muxes can be used to build a single 4-to-1 mux : true / false TRUE e.) A 4-to-16 decoder with an enable can be used as a 1-to-16 demultiplexer : true / false TRUE f.) 5 flip-flops are required to implement a state machine with 5 states : true / false FALSE g.) In a state machine with Moore style outputs, a change in the external inputs can independently and immediately cause the outputs to change : true / false FALSE h.) In binary, performing X- Y can be performed by adding X to the 2’s complement of Y : true / false TRUE i.) The characteristic equation of a JK Flip- flop is Q* = J•Q + K ’• Q : true / false TRUE j.) The passive inputs (hold state) of an active-hi set and reset SR-Latch are S=0, R=0: true / false TRUE
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2.) State Machine Design (Down Counter w/ Restart) : Design a synchronous state machine circuit that implements a 2- bit down counter (i.e. counts 11, 10, 01, 00, 11…). The circuit has an external input, R (RESTART), that when ‘1’ should force the counter back to the 11 state no matter what the current state is. As long as R stays ‘1’, the counter should stay in the 11 state. The circuit should also have one output Z. Z=1 when in the 00 state and Z = 0 otherwise. Let us use 4 states: S3 (initial state on reset) The count should be 11 2 = 3 10 S2 The count should be 10 2 = 2 10 S1 The count should be 01 2 = 1 10 S0 The count should be 00 2 = 0 10 a.) Complete the state diagram below by filling in all necessary transitions and the values of Z.
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This note was uploaded on 01/18/2011 for the course EE 101 taught by Professor Redekopp during the Fall '06 term at USC.

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SampleFinalSol - EE 101 Sample Final Redekopp Name: _ 1.)...

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