ee101_hw6_sol

ee101_hw6_sol - So, for the enab le gates… /CP Input /S...

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EE 101 Homework 6 Redekopp Solutions: 1.a X Y Q P X Y Q* 0 0 ? Hold case if P = Q’ Illegal / Not Stable if Q = P 0 1 ? Illegal / Toggling 1 0 ? Illegal / Toggling 1 1 ? Hold case if P = Q Illegal / Not Stable if Q = P’ 1.b X Y Q X = Set Y = Reset Q* 0 0 Q Hold 0 1 0 Reset 1 0 1 Set 1 1 1 Illegal (Both Set and Reset)
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2. /S /CP (clock pulse) Q Q’ /R NAND gate bistable passive case is 1,1. Thus when CP = 1 (inactive), we want to produce 1,1 at the internals /S and /R inputs. When CP = 0, we want to pass the inputs.
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Unformatted text preview: So, for the enab le gates… /CP Input /S and /R Output of Enable Gate 0 (Enabled) 0 0 0 (Enabled) 1 1 1 (Disabled) 0 1 (Passive) 1 (Disabled) 1 1 (Passive) We’ve just described an OR gate (or drawn to match the active-levels as shown above.) 3. C D Q 4.a. CLK Q D 4.b. CLK Q D 5.a. CLK K J Q Q 5.b. CLK K J Q Q 6. K J Q Q K J Q Q 1 Q0 Q1 CLK CLK Q0 Q1 CK CK 7. D Q Q CK D Q Q CK CLK D0 D1 D2 /D1 /D2 OUT CLK D0 D1 D2 OUT...
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This note was uploaded on 01/18/2011 for the course EE 101 taught by Professor Redekopp during the Fall '06 term at USC.

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ee101_hw6_sol - So, for the enab le gates… /CP Input /S...

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