L3_Instruction Execution

L3_Instruction Execution - Y. Shih Adv Comp Org...

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Unformatted text preview: Y. Shih Adv Comp Org & Structure 1 EE504 Lecture 3 Instruction Execution & Basic Pipelining Concepts Dr. Yifong Shih Northwestern Polytechnic University Spring 2008 Y. Shih Adv Comp Org & Structure 2 Outline Course project CPU design considerations Quick review of multi-cycle, unpipelined CPU design Introduction to pipelining Y. Shih Adv Comp Org & Structure 3 EE504 Project By next lecture, form either a two-men or three-men team and let me know who you are. By March 26 each team must obtain my approval for its project topic and amount of work involved Each team will do a 15-minute presentation on the week April 28 to May 3 Before the final exam each team is expected to turn in a project report (typed, no less than 10 pages, but no more than 20) More on projects in future lectures Readings Appendix A Y. Shih Adv Comp Org & Structure 4 Y. Shih Adv Comp Org & Structure 5 CPU Design Considerations 1 First and foremost, decide on the problem statement: what problem(s) are we trying to solve by designing this processor? General purpose CPU: x86 Backward compatibility Engineering & enterprise: PPC, SPARC Backward compatibility, performance Embedded applications: automobile, cell phone, home appliances Low power consumption, low cost, cores that can be licensed (e.g. ARM, PPC) and embedded in a system-on-chip Special purpose: MPEG, crypto, gigabit ethernet port Performance (operate at line rate?), embedded in SoC, cost Lots of overlaps among areas Y. Shih Adv Comp Org & Structure 6 CPU Design Considerations 2 Once youve decided on the type of processor, youll need to collect data to characterize your design space Benchmarks & workloads Cost dictates die size Power requirement might dictate chip complexity & novel circuit design Available process technology (is 65 nm good enough?) Time to market: license existing processor core or design from scratch? Verification: how many directed test vectors and how many random testing cycles (in the hundreds of billions cycles) do we need? Must find a balance between directed vs. random Y. Shih Adv Comp Org & Structure 7 CPU Design Considerations 3 Hard data points come from experimenting with workloads. They give you directions in ISA. Some basic ISA issues are: Machine word size (32-bit, 64-bit, 128-bit) Instruction usage and addressing modes If designing a brand new ISA, you can still use old ISA data Program locality Register allocation Do I need a large register file? Multiple read/write ports? Issues from lecture 2 If designing a novel architecture, new issues come into play, e.g....
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L3_Instruction Execution - Y. Shih Adv Comp Org...

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