L5_ILP 1 - EE504 Lecture 5 Instruction Level Parallelism...

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Y. Shih “Adv Comp Org & Structures” 1 EE504 Lecture 5 Instruction Level Parallelism Part 1 Superscalar Architectures and Dynamic Hardware Scheduling Dr. Yifong Shih Northwestern Polytechnic University Spring 2008
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Homework Do all examples from page 66 to 86 of text. Write in your own words, not copy from text. Read Chapter 2 Y. Shih “Adv Comp Org & Structures” 2
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Y. Shih “Adv Comp Org & Structures” 3 Outline 1. Instruction and machine parallelism 2. Simple superscalar CPU architecture 3. Instruction Issue and machine parallelism: In-Order Issue with In-Order Completion In-Order Issue with Out-of-Order Completion Out-of-Order Issue with Out-of-Order Completion 4. Machine parallelism and instruction window 5. Introduction to Tomasulo Algorithm 6. Register renaming 7. Reorder buffer
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Y. Shih “Adv Comp Org & Structures” 4 Why Instruction Level Parallelism? So far we’ve looked into ways of improving the basic pipeline to better handle structural, data & control hazards using forwarding/bypassing, branch prediction and simple compiler help thru delay slot scheduling and instruction shuffling… But we have not considered if processing instructions in parallel might help Indeed ILP will help; we just need to figure out how
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Y. Shih “Adv Comp Org & Structures” 5 The Concept of Instruction and  Machine Parallelism Instruction Level Parallelism ( ILP ): Instruction level parallelism is a measure of how many instructions can be executed simultaneously on an infinitely wide superscalar type machine. In other words, how much parallelism is inherent in a piece of code Note the existing parallelism in basic pipelining is still sequential as far as the instruction stream is concerned. From basic pipeline to ILP is analogous to going from a single assembly line to multiple, complex assembly lines Machine level parallelism is how many instructions per cycle we may issue, execute and complete in a given machine architecture MLP constrains the ideal (i.e. maximum) ILP performance
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Y. Shih “Adv Comp Org & Structures” 6 An Example of ILP for(i=0; i<100; i++) array[i] = array[i] + 1; has a considerable amount of parallelism (loop level parallelism) . If we built a machine with 100 functional units and memory ports it would give us a 100x speedup (We are not advocating this ) Fewer branches and dependencies will increase ILP
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Y. Shih “Adv Comp Org & Structures” 7 Machine Parallelism Machine parallelism is the amount of instructional parallelism of which a particular machine implementation is capable of taking advantage Having multiple functional units within CPU supports machine parallelism so that instructions can be issued to them simultaneously
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Y. Shih “Adv Comp Org & Structures” 8 ILP implementation Techniques on  Machine Level Four techniques to improve machine parallelism: 1. Duplication of resources to do more operations and memory accesses 2. Out-of-order instruction issue
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L5_ILP 1 - EE504 Lecture 5 Instruction Level Parallelism...

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